DM505LRBABF datasheet(105/295 Pages) TI2

105 / 295 page

SPRS916_ELCH_06

vdd, vdd_dspeve

xi_osc0

porz

V10

V11

Tdelta2

vdds_ddr1, vdds_ddr2, vdds_dd3

Tdelta1

Note 9

Note 4

Note 7

Note 7, Note 8

Note 6, Note 10

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv5, vddshv6,

vdds18v_ddr3, vdds18v

vdds18v_ddr1, vdds18v_ddr2,

vdda_osc, vdda_per, vdda_ddr_dsp,

vdda_gmac_core, vdda_csi,

vdda_dac, vdda_adc

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv5, vddshv6

Note 5

105

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

Submit Documentation Feedback

Specifications

Figure 5-6 through Figure 5-9 and associated notes described the device Abrupt Power Down Sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally,

the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of

elapsed time. This is the typical range of elapsed time available following a loss of power event, see

Section 7.3.7, Loss of Input Power Event for design recommendations. If sufficient elapse time is not

provided, then an “abrupt” power-down sequence can be supported without impacting POH reliability if all

of the following conditions are met (Figure 5-9).

Figure 5-9. Abrupt Power-Down Sequencing(1)

(1) V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs;

Tdelta2 < 10 ms.

(2) Terminology:

–

VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,

Recommended Operating Conditions.

–

VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.

–

Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.

(3) General timing diagram items:

–

Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.

–

Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit

performance.

(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.

(5) vddshv[1-6] domains supplied by 3.3 V:

–

must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after porz is asserted low.

–

must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).

(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.

(7) vdd_dspeve, vdd, vdds_ddr[1-3], vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.

(8) vdds_ddr* domains:

–

can remain at VOPR MIN or a level greater than vdds18v during ramp down.

–

elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.

(9) vdda_* domains:

DM505LRBABF датащи(PDF) 105 Page - Texas Instruments

DM505LRBABF датащи(HTML) 105 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL