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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM505LRBABF датащи(PDF) 90 Page - Texas Instruments |
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DM505LRBABF датащи(HTML) 90 Page - Texas Instruments |
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90 / 295 page  90 DM505 SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 www.ti.com Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-5. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name UART2 UART2_FCLK Func 192 UART2_GFCLK FUNC_192M_CLK DPLL_PER 48 FUNC_48M_FCLK DPLL_PER UART2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE UART3 UART3_FCLK Func 192 UART3_GFCLK FUNC_192M_CLK DPLL_PER 48 FUNC_48M_FCLK DPLL_PER UART3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE VIP1 PROC_CLK Func 266 VIP1_GCLK L3_ICLK DPLL_CORE L3_CLK Int CORE_ISS_MAIN_ CLK DPLL_CORE L4_CLK Int 133 VIP1_GCLKDIV2 VIP1_GCLK/2 DPLL_CORE 5.6 Power Consumption Summary NOTE Maximum power consumption for this SoC depends on the specific use conditions for the end system. Contact your TI representative for assistance in estimating maximum power consumption for the end system use case. 5.7 Electrical Characteristics NOTE The data specified in Table 5-6 through Table 5-11 are subject to change. NOTE The interfaces or signals described in Table 5-6 through Table 5-11 correspond to the interfaces or signals available in multiplexing mode 0 (Function 1). All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which case different DC electrical characteristics are specified for the different multiplexing modes (Functions). Table 5-6. LVCMOS DDR DC Electrical Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX UNIT Signal Names in MUXMODE 0 (Single-Ended Signals) ABF: ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn[1:0], ddr1_cke[1:0], ddr1_odt[0], ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst, ddr1_ecc_d[7:0], ddr1_dqm_ecc; Driver Mode VOH High-level output threshold (IOH = 0.1 mA) 0.9×VDDS V VOL Low-level output threshold (IOL = 0.1 mA) 0.1×VDDS V CPAD Pad capacitance (including package capacitance) 3 pF |
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