DM505LRBABF datasheet(102/295 Pages) TI2

102 / 295 page

porz

vdds18v_ddr1, vdds18v_ddr2,

vdds18v_ddr3, vdds18v,

vdda_osc, vdda_per, vdda_ddr_dsp,

vdda_gmac_core, vdda_csi,

vdda_dac, vdda_adc

vdds_ddr1, vdds_ddr2, vdds_ddr3

vdd

vdd_dspeve

vddshv1, vddshv2, vddshv3,

vddshv4, vddshv5, vddshv6

xi_osc0

SPRS91 _ELCH_02

Note 6

Note 7

Note 9

Note 10

Note 11

DSPEVE voltage

CORE voltage

EMIF voltage

Note 4

Note 5

Note 8

Note 12

102

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

(7) If any of the vddshv[1-6] power rails are used for 1.8V I/O signaling, then these rails can be combined with vdds18v_*.

If 3.3V I/O signaling is required, then these rails must be the last to ramp following vdd_dspeve.

(8) resetn and porz must remain asserted low for a minimum of 12P(12) after xi_osc0 is stable at a valid frequency.

(9) Setup time: SYSBOOT[15:0] pins must be valid 2P(12) before porz is de-asserted high.

(10) Hold time: SYSBOOT[15:0] pins must be valid 15P(12) after porz is de-asserted high.

(11) resetn to rstoutn delay is 2ms.

(12) P = 1/(SYS_CLK1/610) frequency in ns.

(13) Ramped Up is defined as reaching the minimum operational voltage level for the corresponding power domain. For information about

voltage levels, refer to , Recommended Operating Conditions.

Figure 5-5. Recommended Power-Down Sequencing

(1) T1

≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval

times.

(2) Terminology:

–

VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,

Recommended Operating Conditions.

–

VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.

–

Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.

(3) General timing diagram items:

–

Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.

–

Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.

–

Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit

performance.

(4) porz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.

(5) vddshv[1-6] domains supplied by 3.3 V:

–

must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.

–

must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.

–

must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-6, "vdds18v versus vddshv[1-6] Discharge

Relationship".

(6) vddshv[1-6] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.

(7) vdd_dspeve domain can ramp down before or concurrently with vdd.

(8) vdd must ramp down after or concurrently with vdd_dspeve.

(9) vdds_ddr[1-3] domains:

–

should ramp down after vdd begins ramping down.

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