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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DM505LRBABF датащи(PDF) 87 Page - Texas Instruments |
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DM505LRBABF датащи(HTML) 87 Page - Texas Instruments |
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87 / 295 page  87 DM505 www.ti.com SPRS976E – NOVEMBER 2016 – REVISED MAY 2018 Submit Documentation Feedback Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-5. Maximum Supported Frequency (continued) Module Clock Sources Instance Name Input Clock Name Clock Type Max. Clock Allowed (MHz) PRCM Clock Name PLL / OSC / Source Clock Name PLL / OSC / Source Name MCASP3 MCASP3_AHCLK R Func 50 MCASP7_AHCLK R ABE_24M_GFCLK DPLL_DDR ABE_SYS_CLK SYS_CLK1 FUNC_24M_GFCL K DPLL_PER SYS_CLK1 OSC0 ATL_CLK0 Module ATL ATL_CLK1 Module ATL ATL_CLK2 Module ATL ATL_CLK3 Module ATL SYS_CLK2 OSC1 XREF_CLK0 REF_CLKIN0 XREF_CLK1 REF_CLKIN1 XREF_CLK2 REF_CLKIN2 MCASP3_AHCLKX Func 50 MCASP5_AHCLKX ABE_24M_GFCLK DPLL_DDR ABE_SYS_CLK SYS_CLK1 FUNC_24M_GFCL K DPLL_PER SYS_CLK1 OSC0 ATL_CLK0 Module ATL ATL_CLK1 Module ATL ATL_CLK2 Module ATL ATL_CLK3 Module ATL SYS_CLK2 OSC1 XREF_CLK0 REF_CLKIN0 XREF_CLK1 REF_CLKIN1 XREF_CLK2 REF_CLKIN2 MCASP3_FCLK Func 133 MCASP5_AUX_GF CLK L4_ICLK DPLL_CORE SYS_CLK1 OSC0 MCASP3_ICLK Int 133 L4PER2_L3_GICL K CORE_X2_CLK DPLL_CORE McSPI1 SPI1_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI1_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER McSPI2 SPI2_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI2_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER McSPI3 SPI3_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI3_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER McSPI4 SPI4_ICLK Int 133 L4PER_L3_GICLK CORE_X2_CLK DPLL_CORE SPI4_FCLK Func 48 PER_48M_GFCLK FUNC_192M_CLK DPLL_PER MMC1 MMC_CLK_32K Func 0.032 FUNC_32K_CLK SYS_CLK1/610 OSC0 MMC_FCLK Func 192 MMC4_GFCLK FUNC_192M_CLK DPLL_PER 48 FUNC_48M_FCLK DPLL_PER MMC_ICLK Int 133 L3INIT_L3_GICLK CORE_X2_CLK DPLL_CORE MMU_EDMA MMU_CLK Int 266 L3MAIN1_L3_GIC LK CORE_X2_CLK DPLL_CORE OCMC_RAM OCMC_L3_CLK Int 266 L3MAIN1_L3_GIC LK CORE_X2_CLK DPLL_CORE |
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