DM505LRBABF datasheet(100/295 Pages) TI2

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100

DM505

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Specifications

5.9.1.1.3 Timing Parameters and Board Routing Analysis

The timing parameter values specified in this data manual do not include delays by board routes. As a

good board design practice, such delays must always be taken into account. Timing values may be

adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer

information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS

models to attain accurate timing analysis for a given system, see the Using IBIS Models for timing

Analysis application report (literature number SPRA839). If needed, external logic hardware such as

buffers may be used to compensate any timing differences.

5.9.2

Interface Clock Specifications

5.9.2.1

Interface Clock Terminology

The interface clock is used at the system level to sequence the data and/or to control transfers accordingly

with the interface protocol.

5.9.2.2

Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

•

The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the Device IC and does not take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and the Device IC timing

characteristics as well to define properly the maximum operating frequency that corresponds to the

maximum frequency supported to transfer the data on this interface.

DM505LRBABF датащи(PDF) 100 Page - Texas Instruments