DM505LRBABF datasheet(95/295 Pages) TI2

95 / 295 page

DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

Submit Documentation Feedback

Specifications

Table 5-11. LVCMOS CSI2 DC Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MIN

NOM

MAX

UNIT

VCMRXDC

Differential input common-mode voltage(5)(6)

330

ZID

Differential input impedance

100

125

(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.

(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended

line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.

(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference

between the VITH threshold and the VITL threshold.

(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during

ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.

(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.

(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and

variations below 450 MHz.

(7) This number corresponds to the VODMAX transmitter.

(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.

(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.

(10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-8 CSI 2 Signal Descriptions.

Table 5-12. Dual Voltage LVCMOS DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

1.8-V Mode

VIH

Input high-level threshold

0.65×VDDS

VIL

Input low-level threshold

0.35×VDDS

VHYS

Input hysteresis voltage

100

VOH

Output high-level threshold (IOH = 2 mA)

VDDS-0.45

VOL

Output low-level threshold (IOL = 2 mA)

0.45

IDRIVE

Pin Drive strength at PAD Voltage = 0.45V or VDDS-

0.45V

IIN

Input current at each I/O pin

µA

IOZ

IOZ(IPAD Current) at each IO pin. PAD is swept from 0

to VDDS and the Max(I(PAD)) is measured and is

reported as IOZ

11.5

µA

IIN with pulldown enabled

Input current at each I/O pin with weak pulldown

enabled measured when PAD = VDDS

120

200

µA

IIN with pullup enabled

Input current at each I/O pin with weak pullup enabled

measured when PAD = 0

120

210

µA

CPAD

Pad capacitance (including package capacitance)

Output impedance (drive strength)

3.3-V Mode

VIH

Input high-level threshold

VIL

Input low-level threshold

0.8

VHYS

Input hysteresis voltage

200

VOH

Output high-level threshold (IOH =100µA)

VDDS-0.2

VOL

Output low-level threshold (IOL = 100µA)

0.2

IDRIVE

Pin Drive strength at PAD Voltage = 0.45V or VDDS-

0.45V

IIN

Input current at each I/O pin

µA

IOZ

IOZ(IPAD Current) at each IO pin. PAD is swept from 0

to VDDS and the Max(I(PAD)) is measured and is

reported as IOZ

µA

DM505LRBABF датащи(PDF) 95 Page - Texas Instruments

DM505LRBABF датащи(HTML) 95 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL