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STM32H533CE датащи(PDF) 177 Page - STMicroelectronics |
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STM32H533CE датащи(HTML) 177 Page - STMicroelectronics |
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177 / 231 page ![]() DS14539 Rev 1 177/231 STM32H533xx Electrical characteristics 200 General PCB design guidelines It is recommended to perform power supply decoupling as shown in Figure 44 or Figure 45, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors must be ceramic (good quality), and placed as close as possible to the chip. Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is not available on all packages (refer to Table 15), VREF- is available only on LQFP100 and UFBGA144 packages. When VREF+ is not available, it is internally connected to VSSA. Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is not available on all packages (refer to Table 15), VREF- is available only on LQFP100 and UFBGA144 packages. When VREF- is not available, it is internally connected to VSSA. If VREF- is not available, it is connected internally to VDDA. MSv50648V2 1 μF // 100 nF 1 μF // 100 nF STM32 VREF+ (1) VSSA/VREF- (1) VDDA MSv50649V1 1 μF // 100 nF STM32 VREF+/VDDA (1) VREF-/VSSA (1) |
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