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STM32H533CE датащи(PDF) 176 Page - STMicroelectronics

номер детали STM32H533CE
подробное описание детали  Arm® Cortex®-M33 32-bit MCUTrustZone® FPU, 375 DMIPS 250 MHz, 512-Kbyte flash, 272-Kbyte RAM, cryptography
PDF  231 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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STM32H533CE датащи(HTML) 176 Page - STMicroelectronics

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Electrical characteristics
STM32H533xx
176/231
DS14539 Rev 1
Figure 42. ADC accuracy characteristics
1. Example of an actual transfer curve.
2. Ideal transfer curve.
3. End point correlation line.
4. ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
5. EO = Offset error: deviation between the first actual transition and the first ideal one.
6. EG = Gain error: deviation between the last ideal transition and the last actual one.
7. ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
8. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 43. Typical connection diagram when using the ADC with FT/TT pins
featuring analog switch function
1. Refer to Table 90 for the values of RAIN, and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 57). A high Cparasitic value downgrades conversion accuracy. To remedy
this, fADC should be reduced.
3. Refer to Table 57 for the value of Ilkg.
MSv19880V6
(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End-point correlation line
n = ADC resolution
ET = total unadjusted error: maximum deviation
between the actual and ideal transfer curves
EO = offset error: maximum deviation between the first
actual transition and the first ideal one
EG = gain error: deviation between the last ideal
transition and the last actual one
ED = differential linearity error: maximum deviation
between actual steps and the ideal one
EL = integral linearity error: maximum deviation between
any actual transition and the end point correlation line
2
n-1
7
6
5
4
3
2
1
0
Output code
EO
VSSA
2
n-2
2
n-3
VREF+ (VDDA)
ET
EL
ED
1 LSB ideal
EG
(1)
(2)
(3)
(or
)]
[1LSB =
VDDA
2
n
VREF+
2
n
MSv67871V3
Sample-and-hold ADC converter
Converter
Cparasitic
(2)
Ilkg
(3)
CADC
VDDA
(4)
RAIN
(1)
VAIN
RADC
VREF+
(4)
VSSA
I/O
analog
switch
Sampling
switch with
multiplexing
VSS
VSS



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