SPC563M60L7 datasheet(36/128 Pages) STMICROELECTRONICS

36 / 128 page

Overview

SPC563M64x, SPC563M60x

36/128

DocID14642 Rev 12

2.3.18.2

System Timer Module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as

defined by AUTOSAR (see autosar.org web site). It consists of a single 32-bit counter,

clocked by the system clock, and four independent timer comparators. These comparators

produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:



One 32-bit up counter with 8-bit prescaler



Four 32-bit compare channels



Independent interrupt source for each channel



Counter can be stopped in debug mode

2.3.19

Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the

standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit

modulus counter, clocked by the system clock or the crystal clock, that can provide a system

reset or interrupt request when the correct software key is not written within the required

time window.

The following features are implemented:



32-bit modulus counter



Clocked by system clock or crystal clock



Optional programmable watchdog window mode



Can optionally cause system reset or interrupt request on timeout



Reset by writing a software key to memory mapped register



Enabled out of reset



Configuration is protected by a software key or a write-once register

2.3.20

Debug features

2.3.20.1

Nexus port controller

The NPC (Nexus Port Controller) block provides real-time development support capabilities

for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO

5001-2003 standard. This development support is supplied for MCUs without requiring

external address and data pins for internal visibility. The NPC block is an integration of

several individual Nexus blocks that are selected to provide the development support

interface for SPC563Mxx. The NPC block interfaces to the host processor (e200z335),

eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003

standard. The development support provided includes program trace and run-time access

to the MCUs internal memory map and access to the Power Architecture and eTPU internal

registers during halt. The Nexus interface also supports a JTAG only mode using only the

JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide)

Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable

I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using

calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary

port is available.

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