SPC563M60L7 datasheet(34/128 Pages) STMICROELECTRONICS

34 / 128 page

Overview

SPC563M64x, SPC563M60x

34/128

DocID14642 Rev 12



Automatic parity generation



LIN support

–

Autonomous transmission of entire frames

–

Configurable to support all revisions of the LIN standard

–

Automatic parity bit generation

–

Double stop bit after bit error

–

10- or 13-bit break support



Separately enabled transmitter and receiver



Programmable transmitter output parity



2 receiver wake up methods:

–

Idle line wake-up

–

Address mark wake-up



Interrupt-driven operation with flags



Receiver framing error detection



Hardware parity checking



1/16 bit-time noise detection



DMA support for both transmit and receive data

–

Global error bit stored with receive data in system RAM to allow post processing of

errors

2.3.17

FlexCAN

The SPC563Mxx MCU contains two controller area network (FlexCAN) blocks. The

FlexCAN module is a communication controller implementing the CAN protocol according to

Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a

vehicle serial data bus, meeting the specific requirements of this field: real-time processing,

reliable operation in the EMI environment of a vehicle, cost-effectiveness and required

bandwidth. FlexCAN module ‘A’ contains 64 message buffers (MB); FlexCAN module ‘C’

contains 32 message buffers.

The FlexCAN module provides the following features:



Full Implementation of the CAN protocol specification, Version 2.0B

–

Standard data and remote frames

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Extended data and remote frames

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Zero to eight bytes data length

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Programmable bit rate up to 1 Mbit/s



Content-related addressing



64 / 32 message buffers of zero to eight bytes data length



Individual Rx Mask Register per message buffer



Each message buffer configurable as Rx or Tx, all supporting standard and extended

messages



Includes 1056 / 544 bytes of embedded memory for message buffer storage



Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers



Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

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