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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPC563M60L7 датащи(PDF) 91 Page - STMicroelectronics |
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SPC563M60L7 датащи(HTML) 91 Page - STMicroelectronics |
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91 / 128 page  DocID14642 Rev 12 91/128 SPC563M64x, SPC563M60x Electrical characteristics 127 fsys CC T System frequency in bypass mode(3) Crystal reference 4 20 MHz P External reference 0 80 tCYC CC D System clock period — — 1 / fsys ns fLORL fLORH CC D Loss of reference frequency window(4) Lower limit 1.6 3.7 MHz D Upper limit 24 56 fSCM CC P Self-clocked mode frequency (5),(6) —1.2 75 MHz CJITTER CC T CLKOUT period jitter(7),(8),(9), (10) Peak-to-peak (clock edge to clock edge) fSYS maximum –5 5 % fCLK OUT T Long-term jitter (avg. over 2 ms interval) –6 6 ns tcst CC T Crystal start-up time (11), (12) —— 10 ms VIHEXT CC T EXTAL input high voltage Crystal Mode(13), 0.8 Vxtal 1.5V Vxtal + 0.4 — V T External Reference(13),(14) VRC33/2 + 0.4 VRC33 VILEXT CC T EXTAL input low voltage Crystal Mode(13), 0.65 Vxtal1.25V — Vxtal – 0.4 V T External Reference(13),(14) 0 VRC33/2 – 0.4 — CC T XTAL load capacitance(11) 4 MHz 5 30 pF 8 MHz 5 26 12 MHz 5 23 16 MHz 5 19 20 MHz 5 16 tlpll CC P PLL lock time (11),(15) —— 200 s tdc CC T Duty cycle of reference —40 60 % fLCK CC T Frequency LOCK range — –6 6 % fsys fUL CC T Frequency un-LOCK range — –18 18 % fsys fCS fDS CC D Modulation Depth Center spread ±0.25 ±4.0 %fsys D Down Spread –0.5 –8.0 fMOD CC D Modulation frequency(16) —— 100 kHz 1. Considering operation with PLL not bypassed. 2. fVCO is calculated as follows: — In Legacy Mode fVCO = (fcrystal / (PREDIV + 1)) * (4 * (MFD + 4)) — In Enhanced Mode fvco = (fcrystal / (EPREDIV + 1)) * (EMFD + 4) 3. All internal registers retain data at 0 Hz. 4. “Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode. Table 28. PLLMRFM electrical specifications (VDDPLL =1.14 V to 1.32 V, VSS = VSSPLL = 0 V, TA = TL to TH) (continued) Symbol C Parameter Conditions Value Unit Min Max |
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