SPC563M60L7 datasheet(32/128 Pages) STMICROELECTRONICS

32 / 128 page

Overview

SPC563M64x, SPC563M60x

32/128

DocID14642 Rev 12

The DSPIs have three configurations:



Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16-

bit SPI with support for queues



Enhanced Deserial Serial Interface (DSI) configuration where DSPI serializes up to 32

bits with three possible sources per bit

–

eTPU, eMIOS, new virtual GPIO registers as possible bit source

–

Programmable inter-frame gap in continuous mode

–

Bit source selection allows microsecond channel downstream with command or

data frames up to 32 bits

–

Microsecond channel dual receiver mode



Combined serial interface (CSI) configuration where the DSPI operates in both SPI and

DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI

frames

For queued operations, the SPI queues reside in system memory external to the DSPI. Data

transfers between the memory and the DSPI FIFOs are accomplished through the use of

the eDMA controller or through host software.

The DSPI supports these SPI features:



Full-duplex, synchronous transfers



Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins



Master and Slave Mode



Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries



Buffered receive operation using the RX FIFO with parameterized depth of 4 entries



TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues



Visibility into the TX and RX FIFOs for ease of debugging



FIFO Bypass Mode for low-latency updates to SPI queues



Programmable transfer attributes on a per-frame basis:

–

Parameterized number of transfer attribute registers (from two to eight)

–

Serial clock with programmable polarity and phase

–

Various programmable delays:

PCS to SCK delay

SCK to PCS delay

Delay between frames

–

Programmable serial frame size of 4 to 16 bits, expandable with software control

–

Continuously held chip select capability



6 Peripheral Chip Selects, expandable to 64 with external demultiplexer



Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer



DMA support for adding entries to TX FIFO and removing entries from RX FIFO:

–

TX FIFO is not full (TFFF)

–

RX FIFO is not empty (RFDF)

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