SPC563M60L7 datasheet(30/128 Pages) STMICROELECTRONICS

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Overview

SPC563M64x, SPC563M60x

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DocID14642 Rev 12

were performing when the trigger occurred. The eQADC supports software and external

hardware triggers from other blocks to initiate transfers of commands from the queues to the

on-chip ADCs or to the external device. It also monitors the fullness of command queues

and result queues, and accordingly generates DMA or interrupt requests to control data

movement between the queues and the system memory, which is external to the eQADC.

The ADCs also support features designed to allow the direct connection of high impedance

acoustic sensors that might be used in a system for detecting engine knock. These features

include differential inputs; integrated variable gain amplifiers for increasing the dynamic

range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.

The eQADC also integrates a programmable decimation filter capable of taking in ADC

conversion results at a high rate, passing them through a hardware low pass filter, then

down-sampling the output of the filter and feeding the lower sample rate results to the result

FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of

out-of-band noise; while providing a reduced sample rate output to minimize the amount

DSP processing bandwidth required to fully process the digitized waveform.

The eQADC provides the following features:



Dual on-chip ADCs

–2

 12-bit ADC resolution

–

Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)

12-bit conversion time – 1

s (1M sample/sec)

10-bit conversion time – 867 ns (1.2M sample/second)

8-bit conversion time – 733 ns (1.4M sample/second)

–

Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s

–

Differential conversions

–

Single-ended signal range from 0 to 5 V

–

Variable gain amplifiers on differential inputs (

1, 2, 4)

–

Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

–

Provides time stamp information when requested

–

Parallel interface to eQADC CFIFOs and RFIFOs

–

Supports both right-justified unsigned and signed formats for conversion results



Up to 34(d) input channels (accessible by both ADCs)



23 additional internal channels for measuring control and monitoring voltages inside

the device

–

Including Core voltage, I/O voltage, LVI voltages, etc.



An internal bandgap reference to allow absolute voltage measurements



4 pairs of differential analog input channels

–

Programmable pull-up/pull-down resistors on each differential input for biasing

and sensor diagnostic (200 k

, 100 k, 5 k)



Silicon die temperature sensor

–

provides temperature of silicon as an analog value

–

read using an internal ADC analog channel

176-pin package has 34 input channels; 144-pin package has 32 input channels.

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