SPC563M60L7 datasheet(12/128 Pages) STMICROELECTRONICS

12 / 128 page

Overview

SPC563M64x, SPC563M60x

12/128

DocID14642 Rev 12

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Non-maskable interrupt (NMI) input for handling external events that must

produce an immediate response, e.g., power down detection. On this device, the

NMI input is connected to the Critical Interrupt Input. (May not be recoverable)

–

Critical Interrupt input. For external interrupt sources that are higher priority than

provided by the Interrupt Controller. (Always recoverable)

–

New ‘Wait for Interrupt’ instruction, to be used with new low power modes

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Reservation instructions for implementing read-modify-write accesses

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Signal processing extension (SPE) APU

– Operating on all 32 GPRs that are all extended to 64 bits wide

– Provides a full compliment of vector and scalar integer and floating point

arithmetic operations (including integer vector MAC and MUL operations)

(SIMD)

– Provides rich array of extended 64-bit loads and stores to/from extended

GPRs

– Fully code compatible with e200z6 core

–

Floating point (FPU)

– IEEE 754 compatible with software wrapper

– Scalar single precision in hardware, double precision with software library

– Conversion instructions between single precision floating point and fixed

point

– Fully code compatible with e200z6 core

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Long cycle time instructions, except for guarded loads, do not increase interrupt

latency

–

Extensive system development support through Nexus debug port



Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)

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Three master ports, four slave ports

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Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA

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Slave: Flash; SRAM; Peripheral Bridge; calibration EBI

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32-bit internal address bus, 64-bit internal data bus



Enhanced direct memory access (eDMA) controller

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32 channels support independent 8-bit, 16-bit, or 32-bit single value or block

transfers

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Supports variable sized queues and circular queues

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Source and destination address registers are independently configured to post-

increment or remain constant

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Each transfer is initiated by a peripheral, CPU, or eDMA channel request

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Each eDMA channel can optionally send an interrupt request to the CPU on

completion of a single value or block transfer



Interrupt controller (INTC)

–

191 peripheral interrupt request sources

–

8 software setable interrupt request sources

–

9-bit vector

– Unique vector for each interrupt request source

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