SPC563M60L7 datasheet(29/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Overview

127

–

32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and

subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte

operands, single-bit manipulation, shift operations, sign extension and conditional

execution

–

Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned

Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit

works in parallel with the regular microcode commands



Resource sharing features support channel use of common channel registers, memory

and micro engine time:

–

Hardware scheduler works as a “task management” unit, dispatching event

service routines by predefined, host-configured priority

–

Automatic channel context switch when a “task switch” occurs, i.e., one function

thread ends and another begins to service a request from other channel: channel-

specific registers, flags and parameter base address are automatically loaded for

the next serviced channel

–

SPRAM shared between host CPU and eTPU2, supporting communication either

between channels and host or inter-channel

–

Dual-parameter coherency hardware support allows atomic access to two

parameters by host



Test and development support features:

–

Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction

execution, hardware breakpoints and watchpoints on several conditions

–

Software breakpoints

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SCM continuous signature-check built-in self test (MISC — multiple input

signature calculator), runs concurrently with eTPU2 normal operation



System enhancements

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Software watchdog with programmable timeout

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Real-time performance information



Channel enhancements

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Channels 1 and 2 can optionally drive angle clock hardware



Programming enhancements

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Engine relative addressing mode

2.3.14

eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast

conversions for a wide range of applications. The eQADC provides a parallel interface to

two on-chip analog to digital converters (ADC), and a single master to single slave serial

interface to an off-chip external device. Both on-chip ADCs have access to all the analog

channels.

The eQADC prioritizes and transfers commands from six command conversion command

‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from

the on-chip ADCs or from an off-chip external device into the six result queues, in parallel,

independently of the command queues. The six command queues are prioritized with

Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added

ability to bypass all buffering and queuing and abort a currently running conversion on either

ADC and start a Queue_0 conversion. This means that Queue_0 will always have a

deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs

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