MPC8280 datasheet(206/1386 Pages) FREESCALE

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System Interface Unit (SIU)

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

4-34

Freescale Semiconductor

Table 4-12 describes SIUMCR fields.

Table 4-12. SIUMCR Register Field Descriptions

Bits

Name

Description

BBD

Bus busy disable.

0 ABB/IRQ2 pin is ABB, DBB/IRQ3 pin is DBB

1 ABB/IRQ2 pin is IRQ2, DBB/IRQ3 pin is IRQ3

ESE

External snoop enable. Configures GBL/IRQ1

0 External snooping disabled. (GBL/IRQ1 pin is IRQ1)

1 External snooping enabled. (GBL/IRQ1 pin is GBL)

PBSE

Parity byte select enable.

0 Parity byte select is disabled. GPL4 output of UPM is available for memory control.

1 Parity byte select is enabled. GPL4 pin is used as parity byte select output from the MPC8280.

Note: Should not be set if BRx[DECC] = 00. Refer to Section 11.3.1, “Base Registers (BRx).”

CDIS

Core disable.

0 The MPC8280 core is enabled.

1 The MPC8280 core is disabled. MPC8280 functions as a slave device.

4–5

DPPC

Data parity pins configuration. Note that the additional arbitration lines (EXT_BR2, EXT_BG2,

EXT_DBG2, EXT_BR3, EXT_BG3, and EXT_DBG3) are operational only when ACR[EARB] = 0.

Setting EARB (to choose external arbiter) combined with programming DPPC to 11 deactivates these

lines.

DPPC

DP(0)/RSRV

—

DP(0)

RSRV

EXT_BR2

DP(1)/IRQ1

IRQ1

DP(1)

IRQ1

EXT_BG2

DP(2)/TLBISYNC/IRQ2

IRQ2

DP(2)

TLBISYNC

EXT_DBG2

DP(3)/IRQ3

IRQ3

DP(3)

CKSTP_OUT

EXT_BR3

DP(4)/IRQ4

IRQ4

DP(4)

CORE_SRE

SET

EXT_BG3

DP(5)/TBEN/IRQ5/CINT

IRQ5

DP(5)

TBEN

EXT_DBG3

DP(6)/CSE(0)/IRQ6

IRQ6

DP(6)

CSE(0)

IRQ6

DP(7)/CSE(1)/IRQ7

IRQ7

DP(7)

CSE(1)

IRQ7

6–7

L2CPC

L2 cache pins configuration.

Multiplexing

L2CPC = 00

L2CPC = 01

L2CPC = 10

CI/BADDR(29)/IRQ2

IRQ2

BADDR(29)

WT/BADDR(30)/IRQ3

IRQ3

BADDR(30)

L2_HIT/IRQ4

L2_HIT

IRQ4

—

CPU_BG/BADDR(31)/IRQ5/CINT

CPU_BG

IRQ5

BADDR(31)

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