MPC8280 datasheet(142/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-26

Freescale Semiconductor

entries. Software is responsible for maintaining the consistency of the TLB with memory. The core TLBs

are 64-entry, two-way set-associative caches that contain instruction and data address translations. The

core provides hardware assist for software table search operations through the hashed page table on TLB

misses. Supervisor software can invalidate TLB entries selectively.

For instructions and data that maintain address translations for blocks of memory, the G2_LE core

provides independent eight-entry BAT arrays. These entries define blocks that can vary from 128 Kbytes

to 256 Mbytes. The BAT arrays are maintained by system software. Adding the HID2[HBE] to the G2_LE

enables or disables the four additional pairs of BAT registers. However, regardless of the setting of

HID2[HBE], these BATs are accessible by mfspr and mtspr.

As specified by the PowerPC architecture, the hashed page table is a variable-sized data structure that

defines the mapping between virtual page numbers and physical page numbers. The page table size is a

power of two, and its starting address is a multiple of its size.

As specified by the PowerPC architecture, the page table contains a number of PTEGs. A PTEG contains

eight PTEs of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for

table search operations.

2.7

Instruction Timing

The G_LE2 core is a pipelined superscalar processor core. Because instruction processing is reduced into

a series of stages, an instruction does not require all of the resources of an execution unit at the same time.

For example, after an instruction completes the decode stage, it can pass on to the next stage, while the

subsequent instruction can advance into the decode stage. This improves the throughput of the instruction

flow. For example, it may take three cycles for a single floating-point instruction to execute, but if there

are no stalls in the floating-point pipeline, a series of floating-point instructions can have a throughput of

one instruction per cycle.

The core instruction pipeline has four major pipeline stages, described as follows:

•

The fetch pipeline stage primarily involves retrieving instructions from the memory system and

determining the location of the next instruction fetch. Additionally, if possible, the BPU decodes

branches during the fetch stage and folds out branch instructions before the dispatch stage.

•

The dispatch pipeline stage is responsible for decoding the instructions supplied by the instruction

fetch stage, and determining which of the instructions are eligible to be dispatched in the current

cycle. In addition, the source operands of the instructions are read from the appropriate register file

and dispatched with the instruction to the execute pipeline stage. At the end of the dispatch pipeline

stage, the dispatched instructions and their operands are latched by the appropriate execution unit.

•

In the execute pipeline stage, each execution unit with an executable instruction executes the

selected instruction (perhaps over multiple cycles), writes the instruction's result into the

appropriate rename register, and notifies the completion stage when the execution has finished. In

the case of an internal exception, the execution unit reports the exception to the

completion/write-back pipeline stage and discontinues instruction execution until the exception is

handled. The exception is not signaled until that instruction is the next to be completed. Execution

of most floating-point instructions is pipelined within the FPU allowing up to three instructions to

be executing in the FPU concurrently. The FPU pipeline stages are multiply, add, and

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