MPC8280 datasheet(141/1386 Pages) FREESCALE

141 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-25

2.6

Memory Management

The following subsections describe the memory management unit (MMU) features of the PowerPC

architecture and the G2_LE implementation.

2.6.1

PowerPC Memory Management

The primary functions of the MMU are to translate logical (effective) addresses to physical addresses for

memory accesses and to provide access protection on blocks and pages of memory.

The core generates two types of accesses that require address translation: instruction accesses and data

accesses to memory generated by load and store instructions.

The PowerPC MMU and exception model support demand-paged virtual memory. Virtual memory

management permits execution of programs larger than the size of physical memory; demand-paged

memory implies that individual pages are loaded into physical memory from system memory only when

they are first accessed by an executing program.

The hashed page table is a variable-sized data structure that defines the mapping between virtual page

numbers and physical page numbers. The page table size is a power of two, and its starting address is a

multiple of its size.

The page table contains a number of page table entry groups (PTEGs). A PTEG contains eight page table

entries (PTEs) of 8 bytes each; therefore, each PTEG is 64 bytes long. PTEG addresses are entry points for

table search operations.

Address translations are enabled by setting bits in the MSR. MSR[IR] enables instruction address

translations, and MSR[DR] enables data address translations.

2.6.2

Implementation-Specific MMU Features

The instruction and data memory management units in the G2_LE core provide 4 Gbytes of logical address

space accessible to supervisor and user programs with a 4-Kbyte page size and 256-Mbyte segment size.

Block sizes range from 128 Kbytes to 256 Mbytes and are software selectable. In addition, the core uses

an interim 52-bit virtual address and hashed page tables for generating 32-bit physical addresses. The

MMUs in the G2_LE core rely on the exception processing mechanism for the implementation of the

paged virtual memory environment and for enforcing protection of designated memory areas.

Instruction and data TLBs provide address translation in parallel with the on-chip cache access, incurring

no additional time penalty in the event of a TLB hit. A TLB is a cache of the most recently used page table

System

management

interrupt

01400

A system management interrupt is caused when MSR[EE] = 1 and the SMI input

signal is asserted.

Reserved

01500–02FFF

—

Table 2-5. Exceptions and Conditions (continued)

Exception

Type

Vector Offset

(hex)

Causing Conditions

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