MPC8280 datasheet(138/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-22

Freescale Semiconductor

The PowerPC architecture supports four types of exceptions:

•

Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are

handled precisely; that is, the machine state at the time the exception occurs is known and can be

completely restored. This means that (excluding the trap and system call exceptions) the address

of the faulting instruction is provided to the exception handler and that neither the faulting

instruction nor subsequent instructions in the code stream will complete execution before the

exception is taken. Once the exception is processed, execution resumes at the address of the

faulting instruction (or at an alternate address provided by the exception handler). When an

exception is taken due to a trap or system call instruction, execution resumes at an address provided

by the handler.

•

Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point

exception modes: recoverable and nonrecoverable. Even though the G2_LE core provides a means

to enable the imprecise modes, it implements these modes identically to the precise mode (that is,

all enabled floating-point enabled exceptions are always precise on the core).

•

Asynchronous, maskable—The external, system management interrupt (SMI), and decrementer

interrupts are maskable asynchronous exceptions. When these exceptions occur, their handling is

postponed until the next instruction and any exceptions associated with that instruction complete

execution. If no instructions are in the execution units, the exception is taken immediately upon

determination of the correct restart address (for loading SRR0).

•

Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions: system reset

and the machine check exception. These exceptions may not be recoverable, or may provide a

limited degree of recoverability. All exceptions report recoverability through MSR[RI].

2.5.2

Implementation-Specific Exception Model

As specified by the PowerPC architecture, all processor core exceptions can be described as either precise

or imprecise and either synchronous or asynchronous. Asynchronous exceptions (some of which are

maskable) are caused by events external to the processor’s execution. Synchronous exceptions, which are

all handled precisely by the processor core, are caused by instructions. The processor core exception

classes are shown in Table 2-4.

Although exceptions have other characteristics as well, such as whether they are maskable or

nonmaskable, the distinctions shown in Table 2-4 define categories of exceptions that the processor core

handles uniquely. Note that Table 2-4 includes no synchronous imprecise instructions.

Table 2-4. Exception Classifications for the Processor Core

Synchronous/Asynchronous

Precise/Imprecise

Exception Type

Asynchronous, nonmaskable

Imprecise

Machine check

System reset

Asynchronous, maskable

Precise

External interrupt

Decrementer

System management interrupt

Critical interrupt

Synchronous

Precise

Instruction-caused exceptions

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