MPC8280 datasheet(135/1386 Pages) FREESCALE

135 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-19

2.4.2.1

Data Cache

As shown in Figure 2-6, the data cache is configured as 128 sets of four blocks each. Each block consists

of 32 bytes, two state bits, and an address tag. The two state bits implement the three-state MEI

(modified/exclusive/invalid) protocol. Each block contains eight 32-bit words. Note that the PowerPC

architecture defines the term ‘block’ as a cacheable unit. For the MPC8280’s processor core, the block size

is equivalent to a cache line.

Figure 2-6. Data Cache Organization

Because the processor core data cache tags are single-ported, simultaneous load or store and snoop

accesses cause resource contention. Snoop accesses have the highest priority and are given first access to

the tags, unless the snoop access coincides with a tag write, in which case the snoop is retried and must

rearbitrate for access to the cache. Loads or stores that are deferred due to snoop accesses are executed on

the clock cycle following the snoop.

Because the caches on the processor core are write-back caches, the predominant type of transaction for

most applications is burst-read memory operations, followed by burst-write memory operations, and

single-beat (noncacheable or write-through) memory read and write operations. When a cache block is

filled with a burst read, the critical double word is simultaneously written to the cache and forwarded to

the requesting unit, thus minimizing stalls due to load delays.

Additionally, there can be address-only operations, variants of the burst and single-beat operations, (for

example, global memory operations that are snooped and atomic memory operations), and address retry

activity (for example, when a snooped read access hits a modified line in the cache).

Setting HID0[ABE] causes execution of the dcbf, dcbi, and dcbst instructions to be broadcast onto the

60x bus. The value of ABE does not affect dcbz instructions, which are always broadcast and snooped.

The cache operations are intended primarily for managing on-chip caches. However, the optional

broadcast feature is necessary to allow proper management of a system using an external copyback L2

cache.

The address and data buses operate independently to support pipelining and split transactions during

memory accesses. The processor core pipelines its own transactions to a depth of one level.

Address Tag 1

Address Tag 2

Address Tag 3

Block 1

Block 2

Block 3

128 Sets

Address Tag 0

Block 0

8 Words/Block

State

Words 0–7

State

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