MPC8280 datasheet(131/1386 Pages) FREESCALE

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G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

2-15

Table 2-3 describes the HID2 fields.

2.3.1.2.4

Processor Version Register (PVR)

Software can identify the MPC8280’s processor core by reading the processor version register (PVR). The

processor version number is 0x80822013.

2.3.2

PowerPC Instruction Set and Addressing Modes

All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent

among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This

fixed instruction length and consistent format greatly simplifies instruction pipelining.

2.3.2.1

Calculating Effective Addresses

The effective address (EA) is the 32-bit address computed by the processor when executing a memory

access or branch instruction or when fetching the next sequential instruction.

The PowerPC architecture supports two simple memory addressing modes:

•EA = (rA|0) + offset (including offset = 0) (register indirect with immediate index)

•EA = (rA|0) + rB (register indirect with index)

These simple addressing modes allow efficient address generation for memory accesses. Calculation of the

effective address for aligned transfers occurs in a single clock cycle.

For a memory access instruction, if the sum of the effective address and the operand length exceeds the

maximum effective address, the memory operand is considered to wrap around from the maximum

effective address to effective address 0.

Table 2-3. HID2 Field Descriptions

Bits

Name

Function

0–12

—

Reserved

HBE

High BAT enable. Enables the four additional pairs of BAT registers (IBAT4–IBAT7 and

DBAT4–DBAT7). These BATs are accessible by the mfspr and mtspr instructions regardless of the

setting of HID2[HBE].

—

Reserved

SFP

Speed for low power. Setting SFP reduces power consumption at the cost of reducing the maximum

frequency, which benefits power-sensitive applications that are not frequency-critical.

16–18

IWLCK

Instruction cache way lock. Useful for locking blocks of instructions into the instruction cache for

time-critical applications that require deterministic behavior. See Section 2.4.2.3, “Cache Locking.”

19–23

—

Reserved

24–26

DWLCK Data cache way lock. Useful for locking blocks of data into the data cache for time-critical

applications where deterministic behavior is required. See Section 2.4.2.3, “Cache Locking.”

27–31

—

Reserved

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