MPC8280 datasheet(136/1386 Pages) FREESCALE

136 / 1386 page

G2_LE Core

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

2-20

Freescale Semiconductor

Typically, memory accesses are weakly ordered—sequences of operations, including load/store string and

multiple instructions, do not necessarily complete in the order they begin—maximizing the efficiency of

the internal bus without sacrificing coherency of the data. The processor core allows pending read

operations to precede previous store operations (except when a dependency exists, or in cases where a

non-cacheable access is performed), and provides support for a write operation to precede a previously

queued read data tenure (for example, allowing a snoop push to be enveloped by the address and data

tenures of a read operation). Because the processor can dynamically optimize run-time ordering of

load/store traffic, overall performance is improved.

2.4.2.2

Instruction Cache

The instruction cache also consists of 128 sets of four blocks, and each block consists of 32 bytes, an

address tag, and a valid bit. The instruction cache may not be written to except through a block fill

operation caused by a cache miss. In the processor core, internal access to the instruction cache is blocked

only until the critical load completes.

The processor core supports instruction fetching from other instruction cache lines following the

forwarding of the critical first double word of a cache line load operation. The processor core’s instruction

cache is blocked only until the critical load completes (hits under reloads are allowed). Successive

instruction fetches from the cache line being loaded are forwarded, and accesses to other instruction cache

lines can proceed during the cache line load operation.

The instruction cache is not snooped, and cache coherency must be maintained by software. A fast

hardware invalidation capability is provided to support cache maintenance. The organization of the

instruction cache is very similar to the data cache shown in Figure 2-6.

2.4.2.3

Cache Locking

The processor core supports cache locking, which is the ability to prevent some or all of a microprocessor’s

instruction or data cache from being overwritten. Cache entries can be locked for either an entire cache or

for individual ways within the cache. Entire data cache locking is enabled by setting HID0[DLOCK], and

entire instruction cache locking is enabled by setting HID0[ILOCK]. For more information, refer to the

application note Cache Locking on the G2 Core (order number: AN1767). Cache way locking is controlled

by the IWLCK and DWLCK bits of HID2.

2.4.2.3.1

Entire Cache Locking

When an entire cache is locked, hits within the cache are supplied in the same manner as hits to an

unlocked cache. Any access that misses in the cache is treated as a cache-inhibited access. Cache entries

that are invalid at the time of locking will remain invalid and inaccessible until the cache is unlocked. Once

the cache has been unlocked, all entries (including invalid entries) are available. Entire cache locking is

inefficient if the number of instructions or the size of data to be locked is small compared to the cache size.

2.4.2.3.2

Way Locking

Locking only a portion of the cache is accomplished by locking ways within the cache. Locking always

begins with the first way (way0) and is sequential, that is, it is valid to lock ways 0, 1, and 2 but it is not

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