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PM7366-PI датащи(PDF) 167 Page - PMC-Sierra, Inc

номер детали PM7366-PI
подробное описание детали  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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производитель  PMC [PMC-Sierra, Inc]
домашняя страница  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI датащи(HTML) 167 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
154
Register 0x300 : TMAC Control
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
Unused
X
Bit 14
Unused
X
Bit 13
Unused
X
Bit 12
Unused
X
Bit 11
Unused
X
Bit 10
Unused
X
Bit 9
Unused
X
Bit 8
Unused
X
Bit 7
Unused
X
Bit 6
R/W
TDQ_FRN[1]
0
Bit 5
R/W
TDQ_FRN[0]
0
Bit 4
R/W
TDQ_RDYN[2]
0
Bit 3
R/W
TDQ_RDYN[1]
0
Bit 2
R/W
TDQ_RDYN[0]
0
Bit 1
R/W
CACHE
1
Bit 0
R/W
ENABLE
0
This register provides control of the TMAC block.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
ENABLE:
The transmit DMA controller enable bit (ENABLE) enables the TMAC to accept TDRs from
the TDR Ready Queue and reads packet data from host memory. When ENABLE is set high,
the TMAC is enabled. When ENABLE is set low, the TDR Ready Queue is ignored. Once all
linked lists of TDs built up by the TMAC have been exhausted, no more data will be
transmitted on the TD[31:0] links.



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