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PM7366-PI датащи(PDF) 132 Page - PMC-Sierra, Inc

номер детали PM7366-PI
подробное описание детали  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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производитель  PMC [PMC-Sierra, Inc]
домашняя страница  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI датащи(HTML) 132 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
119
Register 0x204 : RHDL Indirect Channel Data Register #1
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R/W
PROV
0
Bit 14
R/W
CRC[1]
0
Bit 13
R/W
CRC[0]
0
Bit 12
R/W
STRIP
0
Bit 11
R/W
DELIN
0
Bit 10
R
TAVAIL
X
Bit 9
Unused
X
Bit 8
W
FPTR[8]
X
Bit 7
W
FPTR[7]
X
Bit 6
W
FPTR[6]
X
Bit 5
W
FPTR[5]
X
Bit 4
W
FPTR[4]
X
Bit 3
W
FPTR[3]
X
Bit 2
W
FPTR[2]
X
Bit 1
W
FPTR[1]
X
Bit 0
W
FPTR[0]
X
This register contains data read from the channel provision RAM after an indirect read operation
or data to be inserted into the channel provision RAM in an indirect write operation.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
FPTR[8:0]:
The indirect FIFO block pointer (FPTR[8:0]) identifies one of the blocks of the circular linked
list in the partial packet buffer used in the logical FIFO of the current channel. The FIFO
pointer to be written to the channel provision RAM, in an indirect write operation, must be set



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