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PM7366-PI датащи(PDF) 221 Page - PMC-Sierra, Inc

номер детали PM7366-PI
подробное описание детали  FRAME ENGINE AND DATA LINK MANAGER
PDF  286 Pages
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производитель  PMC [PMC-Sierra, Inc]
домашняя страница  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7366-PI датащи(HTML) 221 Page - PMC-Sierra, Inc

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RELEASED
PM7366 FREEDM-8
DATA SHEET
PMC-1970930
ISSUE 4
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
208
Register 0x504 : PMON Receive FIFO Overflow Count
Bit
Type
Function
Default
Bit 31 to
Bit 16
Unused
XXXXH
Bit 15
R
OF[15]
X
Bit 14
R
OF[14]
X
Bit 13
R
OF[13]
X
Bit 12
R
OF[12]
X
Bit 11
R
OF[11]
X
Bit 10
R
OF[10]
X
Bit 9
R
OF[9]
X
Bit 8
R
OF[8]
X
Bit 7
R
OF[7]
X
Bit 6
R
OF[6]
X
Bit 5
R
OF[5]
X
Bit 4
R
OF[4]
X
Bit 3
R
OF[3]
X
Bit 2
R
OF[2]
X
Bit 1
R
OF[1]
X
Bit 0
R
OF[0]
X
This register reports the number of receive FIFO overflow events in the previous accumulation
interval.
Note
This register is not byte addressable. Writing to this register modifies all the bits in the register.
Byte selection using byte enable signals (CBEB[3:0]) are not implemented. However, when all
four byte enables are negated, no access is made to this register.
OF[15:0]:
The OF[15:0] bits reports the number of receive FIFO overflow events that have been
detected since the last time this register was polled. This register is polled by writing to the
FREEDM-8 Master Clock / BERT Activity Monitor and Accumulation Trigger register. The



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