PM7366-PI datasheet(212/286 Pages) PMC

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RELEASED

PM7366 FREEDM-8

DATA SHEET

PMC-1970930

ISSUE 4

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

199

bits as a contiguous stream with arbitrary byte alignment or byte aligned to gaps in TCLK[0] is

controlled by the BSYNC bit.

E1:

The E1 frame structure select bit (E1) configures link #0 for channelised E1 operation when

CEN is set high. TCLK[0] is held quiescent during the FAS and NFAS framing bytes. The

most significant bit of time-slot 1 is placed on TD[0] on the last falling edge of TCLK[0] ahead

of the extended quiescent period. Link data is present at time-slots 1 to 31. When E1 is set

low and CEN is set high, link #0 is configured for channelised T1 operation. TCLK[0] is held

quiescent during the framing bit. The m.s.b. of time-slot 1 is placed on TD[0] on the last

falling edge of TCLK[0] ahead of the extended quiescent period. Link data is present at time-

slots 1 to 24. E1 is ignored when CEN is set low.

BSYNC:

The byte synchronisation enable bit (BSYNC) controls the interpretation of gaps in TCLK[0]

when link #0 is in unchannelised mode (CEN set low). When BSYNC is set high, the data bit

on TD[0] clocked in by a downstream device on the first rising edge of TCLK[0] after an

extended quiescent period is considered to be the most significant bit of a data byte. When

BSYNC is set quiescent , gaps in TCLK[0] carry no special significance. BSYNC is ignored

when CEN is set high.

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