FALXT972MCCA4 datasheet(39/92 Pages) INTEL

39 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

5.6.4

Carrier Sense

Carrier Sense (CRS) is an asynchronous output.

• CRS is always generated when the LXT972M Transceiver receives a packet from the line.

• CRS is also generated when the LXT972M Transceiver is in half-duplex mode when a packet

is transmitted.

Table 14 summarizes the conditions for assertion of carrier sense, data loopback, and collision

signals. Carrier sense is not generated when a packet is transmitted and in full-duplex mode.

5.6.5

Error Signals

When the LXT972M Transceiver is in 100 Mbps mode and receives an invalid symbol from the

network, it asserts RX_ER and drives “0101” on the RXD pins.

The TX_ER function that forces ‘H’ symbols out on the TPOP/TPON twisted pair is not

implemented in the LXT972M Transceiver.

5.6.6

Collision

The LXT972M Transceiver asserts its collision signal asynchronously to any clock whenever the

line state is half-duplex and the transmitter and receiver are active at the same time. Table 14

summarizes the conditions for assertion of carrier sense, data loopback, and collision signals.

Table 14. Carrier Sense, Loopback, and Collision Conditions

Speed

Duplex Condition

Carrier Sense

Test

Loop-

back1, 2

Operational

Loop-

back1, 2

Collision

100

Mbps

Full-Duplex

Receive Only

Yes

None

Half-Duplex

Transmit or Receive

Transmit and Receive

Mbps

Full-Duplex

Receive Only

Yes

None

Half-Duplex,

Transmit or Receive

Yes

Transmit and Receive

Half-Duplex,

Transmit or Receive

Transmit and Receive

1. Test Loopback is enabled when Register bit 0.14 = 1.

2. For descriptions of Test Loopback and Operational Loopback, see Section 5.6.7, “Loopback” on page 40.

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