FALXT972MCCA4 datasheet(76/92 Pages) INTEL

76 / 92 page

Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Table 41 lists control register bits.

Table 41. Control Register - Address 0, Hex 0

Bit

Name

Description

Type 1

Default

0.15

Reset

0 = Normal operation

1 = PHY reset

R/W

0.14

Loopback

0 = Disable loopback mode

1 = Enable loopback mode

R/W

0.13

Speed Selection

0.6

0.13

Speed Selected

R/W

Note 2

10 Mbps

100 Mbps

1000 Mbps (not supported)

Reserved

0.12

Auto-Negotiation

Enable

0 = Disable auto-negotiation process

1 = Enable auto-negotiation process

R/W

Note 2

0.11

Power-Down

0 = Normal operation

1 = Power-down

R/W

0.10

Isolate

0 = Normal operation

1 = Electrically isolate PHY from MII

R/W

0.9

Restart Auto-

Negotiation

0 = Normal operation

1 = Restart auto-negotiation process

R/W

0.8

Duplex Mode

0 = Half-duplex

1 = Full-duplex

R/W

Note 2

0.7

Collision Test

0 = Disable COL signal test

1 = Enable COL signal test

R/W

0.6

Speed Selection

X - 0.6

0.13

Speed Selected

R/W

10 Mbps

100 Mbps

1000 Mbps (not supported)

Reserved

0.5:0

Reserved

Write as ‘0’. Ignore on Read.

R/W

00000

1. R/W = Read/Write

SC = Self Clearing

2. Some bits have their default values determined at reset by hardware configuration pins. For default details

for these bits, see Section 5.4.4, “Hardware Configuration Settings”.

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