FALXT972MCCA4 datasheet(18/92 Pages) INTEL

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Intel

® LXT972M Single-Port 10/100 Mbps PHY Transceiver

Datasheet

Document Number: 302875-005

Revision Date: 27-Oct-2005

Table 8 lists signal descriptions of the LXT972M Transceiver configuration and LED driver pins.

Note:

Pull-up/pull-down resistors of 10k Ohms can be implemented if LEDs are not used in the design.

Table 8.

Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions

LQFP

Pin#

Symbol

Type

Signal Description

RESET_L

Reset.

This active Low input is ORed with the control register Reset

bit (Register bit 0.15). The LXT972M Transceiver reset cycle

is extended to 258

μs (nominal) after reset is de-asserted.

RBIAS

Reference Current Bias.

This pin provides bias current for the internal circuitry. Must

be tied to ground through a 22.1 k

Ω, 1% resistor.

REFCLK/XI

AI and

Reference Clock Input / Crystal Input and Crystal Output.

A 25 MHz crystal oscillator circuit can be connected across XI

and XO. A clock can also be used at XI. Refer to Section

5.3.2, “Clock Requirements” on page 28 in the Functional

Description section.

LED/CFG3

LED/CFG2

LEDCFG1

I/O

LED Drivers 1-3.

These pins drive LED indicators. Each LED can display one

of several available status conditions as selected by the LED

Configuration Register. (For details, see Table 54, “LED

Configuration Register - Address 20, Hex 14” on page 87.)

Configuration Inputs 1-3.

These pins also provide initial configuration settings. (For

details, see Table 13, “Hardware Configuration Settings for

Intel® LXT972M Transceiver” on page 33.)

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