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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FALXT972MCCA4 датащи(PDF) 89 Page - Intel Corporation |
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FALXT972MCCA4 датащи(HTML) 89 Page - Intel Corporation |
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89 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 89 Document Number: 302875-005 Revision Date: 27-Oct-2005 Table 56 lists transmit control bits. Table 56. Transmit Control Register - Address 30, Hex 1E Bit Name Description Type 2 Default 30.15:13 Reserved Write as ‘0’. Ignore on Read. R/W 000 30.12 Transmit Low Power Transmit Low Power 0 = Normal transmission. 1 = Forces the transmitter into low power mode. Also forces a zero-differential transmission. R/W 0 30.11:10 Port Rise Time Control 1 Port Rise Time Control 00 = 3.0 ns (Default) 01 = 3.4 ns 10 = 3.9 ns 11 = 4.4 ns R/W 00 30.9:0 Reserved Ignore on Read. R/W 0000000 000 1. Values are approximations and may vary outside indicated values based upon implementation loading conditions. Not guaranteed. 2. R/W = Read/Write 3. Latch State during Reset is based on the state of hardware configuration pins at RESET_L. |
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