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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FALXT972MCCA4 датащи(PDF) 71 Page - Intel Corporation |
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FALXT972MCCA4 датащи(HTML) 71 Page - Intel Corporation |
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71 / 92 page  Intel ® LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 71 Document Number: 302875-005 Revision Date: 27-Oct-2005 Figure 28. Intel® LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing Figure 29. Intel® LXT972M Transceiver Fast Link Pulse Timing Table 36. Intel® LXT972M Transceiver Auto-Negotiation / Fast Link Pulse Timing Parameter Symbol Min Typ 1 Max Units Test Conditions Clock/Data pulse width t1 – 100 – ns – Clock pulse to Data pulse t2 55.5 – 63.8 μs– Clock pulse to Clock pulse t3 123 – 127 μs– FLP burst width t4 – 2 – ms – FLP burst to FLP burst t5 8 12 24 ms – Clock/Data pulses per burst – 17 – 33 Each clock pulse or data pulse – 1. Typical values are at 25 °C and are for design aid only, not guaranteed, and not subject to production testing. TPOP t1 t1 t2 t3 Clock Pulse Data Pulse Clock Pulse B3464-01 t4 t5 FLP Burst FLP Burst TPOP B3465-01 |
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