XRT86VL34 datasheet(95/156 Pages) EXAR

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XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 79: BLOCK INTERRUPT ENABLE REGISTER (BIER)

HEX ADDRESS: 0XnB01

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

Reserved

For E1 mode only

LBCODE_ENB

R/W

Loopback Code Block interrupt enable

This bit permits the user to either enable or disable the Loopback

Code Interrupt Block for interrupt generation.

Writing a “0” to this register bit will disable the Loopback Code Block

for interrupt generation, all Loopback Code interrupts will be dis-

abled for interrupt generation.

If the user writes a “1” to this register bit, the Loopback Code Inter-

rupts at the “Block Level” will be enabled. However, the individual

Loopback Code interrupts at the “Source Level” still need to be

enabled to in order to generate that particular interrupt to the inter-

rupt pin.

0 - Disables all Loopback Code Interrupt Block interrupt within the

device.

1 - Enables the Loopback Code interrupt at the “Block-Level”.

RXCLKLOSS

R/W

Loss of Recovered Clock Interrupt Enable

This bit permits the user to either enable or disable the Loss of

Recovered Clock Interrupt for interrupt generation.

0 - Disables the Loss of Recovered Clock Interrupt within the device.

1 - Enables the Loss of Recovered Clock interrupt at the “Source-

Level”.

ONESEC_ENB

R/W

One Second Interrupt Enable

This bit permits the user to either enable or disable the One Second

Interrupt for interrupt generation.

0 - Disables the One Second Interrupt within the device.

1 - Enables the One Second interrupt at the “Source-Level”.

HDLC_ENB

R/W

HDLC Block Interrupt Enable

This bit permits the user to either enable or disable the HDLC Block

for interrupt generation.

Writing a “0” to this register bit will disable the HDLC Block for inter-

rupt generation, all HDLC interrupts will be disabled for interrupt

generation.

If the user writes a “1” to this register bit, the HDLC Block interrupt at

the “Block Level” will be enabled. However, the individual HDLC

interrupts at the “Source Level” still need to be enabled in order to

generate that particular interrupt to the interrupt pin.

0 - Disables all SA6 Block interrupt within the device.

1 - Enables the SA6 interrupt at the “Block-Level”.

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