XRT86VL34 datasheet(47/156 Pages) EXAR

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XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR)

HEX ADDRESS:0Xn120

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

TxSyncFrD

R/W

Tx Synchronous fraction data interface

This bit selects whether TxCHCLK or TxSERCLK will be used for fractional

data input if fractional interface is enabled. If TxSERCLK is selected to clock in

fractional data input, TxCHCLK will be used as an enable signal

0 = Fractional data Is clocked into the chip using TxChCLK if fractional data

interface is enabled.

1 = Fractional data is clocked into the chip using TxSerClk. TxChClk is used

as fractional data enable.

NOTE: The Time Slot Identifier Pins (TxChn[4:0]) still indicates the time slot

number if fractional data interface is not enabled. Fractional Interface

can be enabled by setting TxFr1544 to 1

Reserved

TxPLClkEnb/

TxSync Is Low

R/W

Transmit payload clock enable/TxSYNC is Active Low

This exact function of this bit depends on whether the T1 framer is configured

to operate in base rate or high speed modes of operation.

If the T1 framer is configured to operate in base rate - TxPayload Clock:

This bit configures the framer to output a regular clock or a payload clock on

the transmit serial clock (TxSERCLK) pin when TxSERCLK is configured to be

an output.

0 = Configures the framer to output a 1.544MHz clock on the TxSERCLK pin

when TxSERCLK is configured as an output.

1 = Configures the framer to output a 1.544MHz clock on the TxSERCLK pin

when transmitting payload bits. There will be gaps on the TxSERCLK output

pin when transmitting overhead bits.

If the T1 framer is configured to operate in high-speed or multiplexed

modes - TxSYNC is Active Low:

This bit is used to select whether the transmit frame boundary (TxSYNC) is

active low or active high.

0 = Selects TxSync to be active “High”

1 = Selects TxSync to be active “Low”

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