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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XRT86VL34 датащи(PDF) 87 Page - Exar Corporation |
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XRT86VL34 датащи(HTML) 87 Page - Exar Corporation |
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87 / 156 page  XRT86VL34 82 REV. V1.2.0 QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION TABLE 64: PMON RECEIVE SEVERELY ERRORED FRAME COUNTER (RSEFC) HEX ADDRESS: 0Xn904 BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION 7 RSEFC[7] RUR 0 Performance Monitor - Receive Severely Errored frame Counter (8-bit Counter) These Reset-Upon-Read bit fields reflect the cumulative number of instances that Receive Severely Errored Frames have been detected by the T1 Framer since the last read of this register. in T1 mode, Severely Errored Frame is defined as having framing bit errors in contiguous windows. In T1 SF mode, SEF is defined if Ft bits have been received consecutively in errors for 0.75ms or 6 SF frames. In T1 ESF mode, SEF is defined if FPS bit have been received consecutively in errors for 3 ms or 24 ESF frames. 6 RSEFC[6] RUR 0 5 RSEFC[5] RUR 0 4 RSEFC[4] RUR 0 3 RSEFC[3] RUR 0 2 RSEFC[2] RUR 0 1 RSEFC[1] RUR 0 0 RSEFC[0] RUR 0 |
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