XRT86VL34 datasheet(45/156 Pages) EXAR

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XRT86VL34

REV. V1.2.0

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

TABLE 26: PERFORMANCE REPORT CONTROL REGISTER (PRCR)

HEX ADDRESS: 0Xn11D

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

LBO_ADJ_ENB

R/W

Transmit Line Build Out Auto Adjustment:

This bit is used to enable or disable the transmit line build out auto

adjustment feature. When the transmitter of the device is sending

AIS condition, the transmit line build out will automatically be adjust

to one setting lower if this feature is enabled. (Please refer to the

EQC[4:0] bits in register 0x0Fn0 for different settings of Transmit

Line Build Out). This feature is designed to for power saving pur-

poses when an AIS signal is being transmitted.

1 - Enables the transmit line build out auto adjustment feature.

0 - Disables the transmit line build out auto adjustment feature.

NOTE: This feature is only available for T1 short haul applications.

RLOS_OUT_ENB

R/W

RLOS Output Enable:

This bit is used to enable or disable the Receive LOS (RLOS_n) out-

put pins.

0 - Disables the RLOS output pin.

1 - Enables the RLOS output pin.

[5-3] Reserved

Reserved.

C/R_BIt

R/W

C/R Bit Control

This bit allows user to control the value of C/R bit within an outgoing

performance report.

0 - Outgoing C/R bit will be set to’0’

1 - Outgoing C/R bit will be set to’1’

[1:0] APCR

R/W

Automatic Performance Control/Response Report

These bits automatically generates a summary report of the PMON

status so that it can be inserted into an out going LAPD message.

Automatic performance report can be generated every time these

bits transition from ‘b00’ to ‘b01‘or automatically every one second.

The table below describes the different APCR[1:0] bits settings.

APCR[1:0]

SOURCE FOR RECEIVE D/E TIMESLOTS

00/11

No performance report issued

Single performance report is issued when

these bits transitions from ‘b00’ to b’01’.

Automatically issues a performance report

every one second

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