XRT86VL34 datasheet(48/156 Pages) EXAR

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

TxFr1544

R/W

Fractional/Signaling Interface Enabled

This bit is used to enable or disable the transmit fractional data interface, sig-

naling input, as well as the 32MHz transmit clock and the transmit overhead

Signal output.

0 = Configures the 5 time slot identifier pins (TxChn[4:0]) to output the channel

number as usual.

1 = Configures the 5 time slot identifier pins (TxChn[4:0]) to function as the fol-

lowing:

TxChn[0] becomes the Transmit Serial SIgnaling pin (TxSIG_n) for signaling

inputs. Signaling data can now be input from the TxSIG pin if configured

appropriately.

TxChn[1] becomes the Transmit Fractional Data Input pin (TxFrTD_n) for frac-

tional data input. Fractional data can now be input from the TxFrTD pin if con-

figured appropriately.

TxChn[2] becomes the 32 MHz transmit clock output

TxChn[3] becomes the Transmit Overhead Signal which pulses high on the

first bit of each multi-frame.

NOTE:

This bit has no effect in the high speed or multiplexed modes of

operation. In high-speed or multiplexed modes, TxCHN[0] functions

as TxSIGn for signaling input.

TxICLKINV

R/W

Transmit Clock Inversion (Backplane Interface)

This bit selects whether data transition will happen on the rising or falling edge

of the transmit clock.

0 = Selects data transition to happen on the rising edge of the transmit clocks.

1 = Selects data transition to happen on the falling edge of the transmit clocks.

NOTE:

This feature is only available for base rate configuration (i.e. non-

highspeed, and non-multiplexed modes).

TxMUXEN

R/W

Multiplexed Mode Enable

This bit enables or disables the multiplexed mode. When multiplexed mode is

enable, multiplexed data of four channels at 12.352 or 16.384MHz are demul-

tiplexed inside the transmit framer and sent to 4 channels on the line side. The

backplane speed will be running at either 12.352 or 16.384MHz depending on

the multiplexed mode selected by TxIMODE[1:0] of this register.

0 = Disables the multiplexed mode.

1 = Enables the multiplexed mode.

TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR)

HEX ADDRESS:0Xn120

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

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