XRT86VL34 datasheet(84/156 Pages) EXAR

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

TABLE 58: LAPD BUFFER 0 CONTROL REGISTER (LAPDBCR0)

HEX ADDRESS: 0Xn600

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-0

LAPD Buffer 0

R/W

LAPD Buffer 0 (96-Bytes) Auto Incrementing

This register is used to transmit and receive LAPD messages within

buffer 0 of the HDLC controller. Any one of the three HDLC control-

ler can be chosen in the LAPD Select Register (0xn11B). Users

should determine the next available buffer by reading the BUFAVAL

bit (bit 7 of the Transmit Data Link Byte Count Register 1 (address

0xn114), Register 2 (0xn144) and Register 3 (0xn154) depending on

which HDLC controller is selected. If buffer 0 is available, writing to

buffer 0 will insert the message into the outgoing LAPD frame after

the LAPD message is sent and the data from the transmit buffer

cannot be retrieved.

After detecting the Receive end of transfer interrupt (RxEOT), users

should read the RBUFPTR bit (bit 7 of the Receive Data Link Byte

Count Register 1 (address 0xn115), Register 2 (0xn145), or Regis-

ter 3 (0xn155) depending on which HDLC controller is selected) to

determine which buffer contains the received LAPD message ready

to be read. If RBUFPTR bit indicates that buffer 0 is available to be

read, reading buffer 0 (Register 0xn600) continuously will retrieve

the entire received LAPD message.

NOTE:

When writing to or reading from Buffer 0, the register is

automatically incremented such that the entire 96 Byte

LAPD message can be written into or read from buffer 0

(Register 0xn600) continuously.

TABLE 59: LAPD BUFFER 1 CONTROL REGISTER (LAPDBCR1)

HEX ADDRESS: 0Xn700

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-0

LAPD Buffer 1

R/W

LAPD Buffer 1 (96-Bytes) Auto Incrementing

This register is used to transmit and receive LAPD messages within

buffer 1 of the HDLC controller. Any one of the three HDLC control-

ler can be is chosen in the LAPD Select Register (0xn11B). Users

should determine the next available buffer by reading the BUFAVAL

bit (bit 7 of the Transmit Data Link Byte Count Register 1 (address

0xn114), Register 2 (0xn144) and Register 3 (0xn154) depending on

which HDLC controller is selected. If buffer 1 is available, writing to

buffer 1 will insert the message into the outgoing LAPD frame after

the LAPD message is sent and the data from the transmit buffer 1

cannot be retrieved.

After detecting the Receive end of transfer interrupt (RxEOT), users

should read the RBUFPTR bit (bit 7 of the Receive Data Link Byte

Count Register 1 (address 0xn115), Register 2 (0xn145), or Regis-

ter 3 (0xn155) depending on which HDLC controller is selected) to

determine which buffer contains the received LAPD message ready

to be read. If RBUFPTR bit indicates that buffer 1 is available to be

read, reading buffer 1 (Register 0xn700) continuously will retrieve

the entire received LAPD message.

NOTE:

When writing to or reading from Buffer 0, the register is

automatically incremented such that the entire 96 Byte

LAPD message can be written into or read from buffer 0

(Register 0xn600) continuously.

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