XRT86VL34 datasheet(40/156 Pages) EXAR

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XRT86VL34

QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

REV. V1.2.0

SB_ENB(1)

R/w

Receive Slip Buffer Mode Select

These bits select modes of operation for the receive slip buffer. These two

bits also select the direction of RxSERCLK and RxSYNC in base clock rate

(2.048MHz). The following table shows the corresponding slip buffer modes

as well as the direction of the RxSYNC/RxSERCLK according to the setting

of these two bits.

NOTE: Users must make sure that the RxSerClk input pin is synchronized to

the Recovered Clock signal for this particular channel to prevent any

buffer slips from occurring.

SB_ENB(0)

R/W

TABLE 20: FIFO LATENCY REGISTER (FFOLR)

HEX ADDRESS: 0Xn117

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

7-5

Reserved

4-0

Rx Slip Buffer FIFO

Latency[4:0]

R/W

00100

Receive Slip Buffer FIFO Latency[4:0]:

These bits permit the user to specify the “Receive Data” Latency (in

terms of RxSerClk_n clock periods), whenever the Receive Slip

Buffer has been configured to operate in the “FIFO” Mode.

NOTE: These bits are only active if the Receive Slip Buffer has been

configured to operate in the FIFO Mode.

TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR)

HEX ADDRESS: 0Xn116

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

SB_ENB

[1:0]

RECEIVE SLIP BUFFER

MODE SELECT

DIRECTION OF

RXSERCLK

DIRECTION OF

RXSYNC

00/11

Receive Slip Buffer is

bypassed

Output

Slip Buffer Mode

Input

Depends on the

setting of SB_SDIR

(bit 2 of this register)

If SB_SDIR = 0:

RxSYNC = Output

If SB_SDIR = 1:

RxSYNC = Input

FIFO Mode.

FIFO data latency

can be programmed

by the 'FIFO Latency

0xn117).

Input

Depends on the

setting of SB_SDIR

(bit 2 of this register)

If SB_SDIR = 0:

RxSYNC = Output

If SB_SDIR = 1:

RxSYNC = Input

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