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AD9516-2/PCBZ датащи(PDF) 12 Page - Analog Devices |
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AD9516-2/PCBZ датащи(HTML) 12 Page - Analog Devices |
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12 / 84 page ![]() AD9516-2 Rev. 0 | Page 12 of 84 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter Min Typ Max Unit Test Conditions/Comments DELAY BLOCK ADDITIVE TIME JITTER1 Incremental additive jitter 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 000000 0.54 ps rms Delay (1600 μA, 1C) Fine Adj. 101111 0.60 ps rms Delay (800 μA, 1C) Fine Adj. 000000 0.65 ps rms Delay (800 μA, 1C) Fine Adj. 101111 0.85 ps rms Delay (800 μA, 4C) Fine Adj. 000000 0.79 ps rms Delay (800 μA, 4C) Fine Adj. 101111 1.2 ps rms Delay (400 μA, 4C) Fine Adj. 000000 1.2 ps rms Delay (400 μA, 4C) Fine Adj. 101111 2.0 ps rms Delay (200 μA, 1C) Fine Adj. 000000 1.3 ps rms Delay (200 μA, 1C) Fine Adj. 101111 2.5 ps rms Delay (200 μA, 4C) Fine Adj. 000000 1.9 ps rms Delay (200 μA, 4C) Fine Adj. 101111 3.8 ps rms 1 This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. SERIAL CONTROL PORT Table 14. Parameter Min Typ Max Unit Test Conditions/Comments CS (INPUT) CS has an internal 30 kΩ pull-up resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 3 μA Input Logic 0 Current 110 μA Input Capacitance 2 pF SCLK (INPUT) SCLK has an internal 30 kΩ pull-down resistor Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 110 μA Input Logic 0 Current 1 μA Input Capacitance 2 pF SDIO (WHEN INPUT) Input Logic 1 Voltage 2.0 V Input Logic 0 Voltage 0.8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO, SDO (OUTPUTS) Output Logic 1 Voltage 2.7 V Output Logic 0 Voltage 0.4 V |
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