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AD9516-2/PCBZ датащи(PDF) 5 Page - Analog Devices

номер детали AD9516-2/PCBZ
подробное описание детали  14-Output Clock Generator with Integrated 2.2 GHz VCO
PDF  84 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9516-2/PCBZ датащи(HTML) 5 Page - Analog Devices

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AD9516-2
Rev. 0 | Page 5 of 84
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
100
MHz
Antibacklash pulse width = 1.3 ns, 2.9 ns
45
MHz
Antibacklash pulse width = 6.0 ns
Antibacklash Pulse Width
1.3
ns
0x17<1:0> = 01b
2.9
ns
0x17<1:0> = 00b; 0x17<1:0> = 11b
6.0
ns
0x17<1:0> = 10b
CHARGE PUMP (CP)
ICP Sink/Source
Programmable
High Value
4.8
mA
With CPRSET = 5.1 kΩ
Low Value
0.60
mA
Absolute Accuracy
2.5
%
VCP = VCP/2
CPRSET Range
2.7/10
ICP High Impedance Mode Leakage
1
nA
Sink-and-Source Current Matching
2
%
0.5 < VCP < VCP − 0.5 V
ICP vs. VCP
1.5
%
0.5 < VCP < VCP − 0.5 V
ICP vs. Temperature
2
%
VCP = VCP/2 V
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
300
MHz
P = 2 FD
600
MHz
P = 3 FD
900
MHz
P = 2 DM (2/3)
600
MHz
P = 4 DM (4/5)
1000
MHz
P = 8 DM (8/9)
2400
MHz
P = 16 DM (16/17)
3000
MHz
P = 32 DM (32/33)
3000
MHz
Prescaler Output Frequency
300
MHz
A, B counter input frequency (prescaler
input frequency divided by P)
PLL DIVIDER DELAYS
Register 0x19: R<5:3>, N<2:0>; see Table 52
000
off
ps
001
330
ps
010
440
ps
011
550
ps
100
660
ps
101
770
ps
110
880
ps
111
990
ps
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Means Within the LBW
of the PLL)
The PLL in-band phase noise floor is estimated
by measuring the in-band phase noise at the
output of the VCO and subtracting 20 log(N)
(where N is the value of the N divider)
@ 500 kHz PFD Frequency
−165
dBc/Hz
@ 1 MHz PFD Frequency
−162
dBc/Hz
@ 10 MHz PFD Frequency
−151
dBc/Hz
@ 50 MHz PFD Frequency
−143
dBc/Hz
PLL Figure of Merit (FOM)
−220
dBc/Hz
Reference slew rate > 0.25 V/ns. FOM +10 log(fPFD)
is an approximation of the PFD/CP in-band
phase noise (in the flat region) inside the PLL
loop bandwidth; when running closed loop,
the phase noise, as observed at the VCO output,
is increased by 20 log(N)



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