AD9516-2SLASHPCBZ datasheet(61/84 Pages) AD

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AD9516-2

Rev. 0 | Page 61 of 84

Table 53. PLL

Reg.

Addr

(Hex) Bit(s) Name

Description

<7>

PFD Polarity Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only.

The on-chip VCO requires positive polarity <7> = 0.

<7> = 0; positive (higher control voltage produces higher frequency).

<7> = 1; negative (higher control voltage produces lower frequency).

<6:4> CP Current

Charge pump current (with CPRSET = 5.1 kΩ).

<6> <5> <4>

ICP (mA)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8

<3:2> CP Mode

Charge pump operating mode.

<3>

<2>

Charge Pump Mode

High impedance state.

Force source current (pump up).

Force sink current (pump down).

Normal operation.

<1:0> PLL Power-

PLL operating mode.

Down

<1>

<0>

Mode

Normal operation.

Asynchronous power-down.

Normal operation.

Synchronous power-down.

<7:0> 14-Bit

R Divider

Bits<7:0>

(LSB)

R divider LSBs—lower eight bits.

<5:0> 14-Bit

R Divider

Bits<13:8>

(MSB)

R divider MSBs—upper six bits.

<5:0> 6-Bit

A Counter

A counter (part of N divider).

<7:0> 13-Bit

B Counter

Bits<7:0>

(LSB)

B counter (part of N divider)—lower eight bits.

<4:0> 13-Bit

B Counter

Bits<12:8>

(MSB)

B counter (part of N divider)—upper five bits.

<7>

Set CP Pin

Set the CP pin to one-half of the VCP supply voltage.

to VCP/2

<7> = 0; CP normal operation.

<7> = 1; CP pin set to VCP/2.

<6>

Reset R

Reset R counter (R divider).

Counter

<6> = 0; normal.

<6> = 1; reset R counter.

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