AD9516-2SLASHPCBZ datasheet(44/84 Pages) AD

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AD9516-2

Rev. 0 | Page 44 of 84

Phase Offset or Coarse Time Delay (0, 1, and 2)

Each channel divider allows for a phase offset, or a coarse time

delay, to be programmed by setting register bits (see Table 38).

These settings determine the number of cycles (successive

rising edges) of the channel divider input frequency by which to

offset, or delay, the rising edge of the output of the divider. This

delay is with respect to a nondelayed output (that is, with a

phase offset of zero). The amount of the delay is set by 5 bits

loaded into the phase offset (PO) register plus the start high

(SH) bit for each channel divider. When the start high bit is set,

the delay is also affected by the number of low cycles (M)

programmed for the divider.

It is necessary to use the SYNC function to make phase offsets

effective (See the Synchronizing the Outputs—SYNC Function

section).

Table 38. Setting Phase Offset and Division for Divider 0,

Divider 1, and Divider 2

Divider

Start

High (SH)

Phase

Offset (PO)

Low Cycles

High Cycles

0x191<4>

0x191<3:0>

0x190<7:4>

0x190<3:0>

0x194<4>

0x194<3:0>

0x193<7:4>

0x193<3:0>

0x197<4>

0x197<3:0>

0x196<7:4>

0x196<3:0>

Let

Δt = delay (in seconds).

Δc = delay (in cycles of clock signal at input to DX).

TX = period of the clock signal at the input of the divider, DX (in

seconds).

Φ =

16 × SH<4> + 8 × PO<3> + 4 × PO<2> + 2 × PO<1> + 1 × PO<0>

The channel divide-by is set as N = high cycles and M = low

cycles.

Case 1

For Φ ≤ 15:

Δt = Φ × TX

Δc = Δt/TX = Φ

Case 2

For Φ ≥ 16:

Δt = (Φ − 16 + M + 1) × TX

Δc = Δt/TX

By giving each divider a different phase offset, output-to-output

delays can be set in increments of the channel divider input

clock cycle. Figure 53 shows the results of setting such a coarse

offset between outputs.

CHANNEL DIVIDER OUTPUTS

DIV = 4, DUTY = 50%

234

567

89 10 11 12 13 14 15

DIVIDER 0

DIVIDER 1

DIVIDER 2

CHANNEL

DIVIDER INPUT

SH = 0

PO = 0

SH = 0

PO = 1

SH = 0

PO = 2

1 × Tx

2 × Tx

Figure 53. Effect of Coarse Phase Offset (or Delay)

Channel Dividers—LVDS/CMOS Outputs

Channel Divider 3 and Channel Divider 4 each drive a pair of

LVDS outputs, giving four LVDS outputs (OUT6 to OUT9).

Alternatively, each of these LVDS differential outputs can be

configured individually as a pair (A and B) of CMOS single-

ended outputs, providing for up to eight CMOS outputs. By

default, the B output of each pair is off but can be turned on as

desired.

Channel Divider 3 and Channel Divider 4 each consist of two

cascaded, 1 to 32, frequency dividers. The channel frequency

division is DX.1 × DX.2 or up to 1024. Both of the dividers also

have DCC enabled by default, but this function can be disabled,

if desired, by setting the DCCOFF bit of the channel. A coarse

phase offset or delay is also programmable (see the Phase Offset

or Coarse Time Delay (Divider 3 and Divider 4) section). The

channel dividers operate up to 1600 MHz. The features and

settings of the dividers are selected by programming the

appropriate setup and control registers (see Table 51 and Table

52 through Table 61).

Table 39. Setting Division (DX) for Divider 3 and Divider 4

Divider

Bypass

DCCOFF

3.1

0x199<7:4>

0x199<3:0>

0x19C<4>

0x19D<0>

3.2

0x19B<7:4>

0x19B<3:0>

0x19C<5>

0x19D<0>

4.1

0x19E<7:4>

0x19E<3:0>

0x1A1<4>

0x1A2<0>

4.2

0x1A0<7:4>

0x1A0<3:0>

0x1A1<5>

0x1A2<0>

Channel Frequency Division (Divider 3 and Divider 4)

The division for each channel divider is set by the bits in the

registers for the individual dividers (X.Y = 3.1, 3.2, 4.1, and 4.2).

Number of Low Cycles = MX.Y + 1

Number of High Cycles = NX.Y + 1

When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1.

When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1.

When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) ×

(NX.2 + MX.2 + 2).

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