AD9516-2SLASHPCBZ datasheet(43/84 Pages) AD

43 / 84 page

AD9516-2

Rev. 0 | Page 43 of 84

Duty Cycle and Duty-Cycle Correction (0, 1, and 2)

The duty cycle of the clock signal at the output of a channel is a

result of some or all of the following conditions:

• What are the M and N values for the channel?

• Is the DCC enabled?

• Is the VCO divider used?

• What is the CLK input duty cycle? (The internal VCO has a

50% duty cycle.)

The DCC function is enabled by default for each channel

divider. However, the DCC function can be disabled

individually for each channel divider by setting the

DCCOFF bit for that channel.

Certain M and N values for a channel divider result in a non-

50% duty cycle. A non-50% duty cycle can also result with an

even division, if M ≠ N. The duty-cycle correction function

automatically corrects non-50% duty cycles at the channel

divider output to 50% duty cycle. Duty-cycle correction

requires the following channel divider conditions:

• An even division must be set as M = N

• An odd division must be set as M = N + 1

When not bypassed or corrected by the DCC function, the duty

cycle of each channel divider output is the numerical value of

(N + 1)/(N + M + 2) expressed as a %.

The duty cycle at the output of the channel divider for various

configurations is shown in Table 35 to Table 37.

Table 35. Duty Cycle with VCO Divider, Input Duty Cycle Is 50%

Output Duty Cycle

VCO

Divider

N + M + 2

DCCOFF = 1

DCCOFF = 0

Even

1 (divider

bypassed)

50%

Odd = 3

1 (divider

bypassed)

33.3%

50%

Odd = 5

1 (divider

bypassed)

40%

50%

Even, Odd

Even

(N + 1)/

(N + M + 2)

50%; requires M = N

Even, Odd

Odd

(N + 1)/

(N + M + 2)

50%; requires M = N + 1

Table 36. Duty Cycle with VCO Divider, Input Duty Cycle Is X%

Output Duty Cycle

VCO

Divider

N + M + 2

DCCOFF = 1

DCCOFF = 0

Even

1 (divider

bypassed)

50%

Odd = 3

1 (divider

bypassed)

33.3%

(1 + X%)/3

Odd = 5

1 (divider

bypassed)

40%

(2 + X%)/5

Even

(N + 1)/

(N + M + 2)

50%,

requires M = N

Odd

(N + 1)/

(N + M + 2)

50%,

requires M = N + 1

Odd = 3

Even

(N + 1)/

(N + M + 2)

50%,

requires M = N

Odd = 3

Odd

(N + 1)/

(N + M + 2)

(3N + 4 + X%)/(6N + 9),

requires M = N + 1

Odd = 5

Even

(N + 1)/

(N + M + 2)

50%,

requires M = N

Odd = 5

Odd

(N + 1)/

(N + M + 2)

(5N + 7 + X%)/(10N + 15),

requires M = N + 1

Table 37. Channel Divider Output Duty Cycle When the

VCO Divider Is Not Used

Output Duty Cycle

Input Clock

Duty Cycle

N + M + 2

DCCOFF = 1

DCCOFF = 0

Any

1 (divider

bypassed)

Same as input

duty cycle

Any

Even

(N + 1)/

(M + N + 2)

50%, requires M = N

50%

Odd

(N + 1)/

(M + N + 2)

50%, requires

M = N + 1

Odd

(N + 1)/

(M + N + 2)

(N + 1 + X%)/(2 × N + 3),

requires M = N + 1

The internal VCO has a duty cycle of 50%. Therefore, when the

VCO is connected directly to the output, the duty cycle is 50%.

If the CLK input is routed directly to the output, the duty cycle of

the output is the same as the CLK input.

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