AD9516-2SLASHPCBZ datasheet(62/84 Pages) AD

62 / 84 page

AD9516-2

Rev. 0 | Page 62 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

<5>

Reset A and B Reset A and B counters (part of N divider).

Counters

<5> = 0; normal.

<5> = 1; reset A and B counters.

<4>

Reset All

Reset R, A, and B counters.

Counters

<4> = 0; normal.

<4> = 1; reset R, A, and B counters.

<3>

B Counter

B counter bypass. This is valid only when operating the prescaler in FD mode.

Bypass

<3> = 0; normal.

<3> = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for

the N divider.

<2:0> Prescaler P

Prescaler: DM = dual modulus and FD = fixed divide.

<2>

<1>

<0> Mode

Prescaler

Divide-by-1.

Divide-by-2.

Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.

Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.

Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.

Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.

Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0.

Divide-by-3.

<7:2> STATUS

Select the signal that is connected to the STATUS pin

Pin Control

<7>

<6> <5> <4>

<3>

<2>

Level or

Dynamic

Signal

Signal at STATUS Pin

LVL

Ground (dc).

DYN

N divider output (after the delay).

DYN

R divider output (after the delay).

DYN

A divider output.

DYN

Prescaler output.

DYN

PFD up pulse.

DYN

PFD down pulse.

LVL

Ground (dc); for all other cases of 0XXXXX not specified above.

The selections that follow are the same as REFMON.

LVL

Ground (dc).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (N/A in differential mode).

DYN

Selected reference to PLL (differential reference when in

differential mode).

DYN

Unselected reference to PLL (not available in differential

mode).

LVL

Status of selected reference (status of differential reference);

active high.

LVL

Status of unselected reference (not available in differential

mode); active high.

LVL

Status REF1 frequency (active high).

LVL

Status REF2 frequency (active high).

LVL

(Status REF1 frequency) AND (status REF2 frequency).

LVL

(DLD) AND (status of selected reference) AND (status of VCO).

LVL

Status of VCO frequency (active high).

LVL

Selected reference (low = REF1, high = REF2).

LVL

Digital lock detect (DLD); active high.

LVL

Holdover active (active high).

AD9516-2/PCBZ датащи(PDF) 62 Page - Analog Devices

AD9516-2/PCBZ датащи(HTML) 62 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL