AD9516-2SLASHPCBZ datasheet(77/84 Pages) AD

77 / 84 page

AD9516-2

Rev. 0 | Page 77 of 84

Reg.

Addr

(Hex)

Bit(s)

Name

Description

1A1

<5>

Bypass Divider 4.2

Bypass (and power down) 4.2 divider logic, route clock to 4.2 output.

<5> = 0; do not bypass.

<5> = 1; bypass.

1A1

<4>

Bypass Divider 4.1

Bypass (and power down) 4.1 divider logic, route clock to 4.1 output.

<4> = 0; do not bypass.

<4> = 1; bypass.

1A1

<3>

Divider 4 Nosync

Nosync.

<3> = 0; obey chip-level SYNC signal.

<3> = 1; ignore chip-level SYNC signal.

1A1

<2>

Divider 4 Force High

Force Divider 4 output high. Requires that nosync also be set.

<2> = 0; force low.

<2> = 1; force high.

1A1

<1>

Start High Divider 4.2

Divider 4.2 start high/low.

<1> = 0; start low.

<1> = 1; start high.

1A1

<0>

Start High Divider 4.1

Divider 4.1 start high/low.

<0> = 0; start low.

<0> = 1; start high.

1A2

<0>

Divider 4 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

Table 59. VCO Divider and CLK Input

Reg.

Addr

(Hex) Bit(s) Name

Description

1E0

<2:0> VCO Divider

<2>

<1>

<0>

Divide

Output static

1E1

<4>

Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).

<4> = 0; normal operation.

<4> = 1; power-down.

1E1

<3>

Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution.

<3> = 0; normal operation.

<3> = 1; power-down.

1E1

<2>

Power-Down VCO and CLK

Power down both VCO and CLK input.

<2> = 0; normal operation.

<2> = 1; power-down.

1E1

<1>

Select VCO or CLK

Select either the VCO or the CLK as the input to VCO divider.

<1> = 0; select external CLK as input to VCO divider.

<1> = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.

1E1

<0>

Bypass VCO Divider

Bypass or use the VCO divider.

<0> = 0; use VCO divider.

<0> = 1; bypass VCO divider; cannot select VCO as input when this is selected.

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