AD9516-2SLASHPCBZ datasheet(75/84 Pages) AD

75 / 84 page

AD9516-2

Rev. 0 | Page 75 of 84

Reg.

Addr

(Hex) Bit(s) Name

Description

192

<1>

Divider 0 Direct to Output

Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.

<1> = 0: OUT0 and OUT1 are connected to Divider 0.

<1> = 1:

If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT0 and OUT1.

If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT0 and OUT1.

If 0x1E1<1:0> = 01b, there is no effect.

192

<0>

Divider 0 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

193

<7:4> Divider 1 Low Cycles

Number of clock cycles of the divider input during which divider output stays low.

193

<3:0> Divider 1 High Cycles

Number of clock cycles of the divider input during which divider output stays high.

194

<7>

Divider 1 Bypass

Bypass and power down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

194

<6>

Divider 1 Nosync

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

194

<5>

Divider 1 Force High

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

194

<4>

Divider 1 Start High

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

194

<3:0> Divider 1 Phase Offset

Phase offset.

195

<1>

Divider 1 Direct to Output

Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.

<1> = 0; OUT2 and OUT3 are connected to Divider 1.

<1> = 1:

If 0x1E1<1:0> = 10b, the VCO is routed directly to OUT2 and OUT3.

If 0x1E1<1:0> = 00b, the CLK is routed directly to OUT2 and OUT3.

If 0x1E1<1:0> = 01b, there is no effect.

195

<0>

Divider 1 DCCOFF

Duty-cycle correction function.

<0> = 0; enable duty-cycle correction.

<0> = 1; disable duty-cycle correction.

196

<7:4> Divider 2 Low Cycles

Number of clock cycles of the divider input during which divider output stays low.

196

<3:0> Divider 2 High Cycles

Number of clock cycles of the divider input during which divider output stays high.

197

<7>

Divider 2 Bypass

Bypass and power down the divider; route input to divider output.

<7> = 0; use divider.

<7> = 1; bypass divider.

197

<6>

Divider 2 Nosync

Nosync.

<6> = 0; obey chip-level SYNC signal.

<6> = 1; ignore chip-level SYNC signal.

197

<5>

Divider 2 Force High

Force divider output to high. This requires that nosync also be set.

<5> = 0; divider output forced to low.

<5> = 1; divider output forced to high.

197

<4>

Divider 2 Start High

Selects clock output to start high or start low.

<4> = 0; start low.

<4> = 1; start high.

197

<3:0> Divider 2 Phase Offset

Phase offset.

AD9516-2/PCBZ датащи(PDF) 75 Page - Analog Devices

AD9516-2/PCBZ датащи(HTML) 75 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL