LP87702 datasheet(29/99 Pages) TI

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Table 8-4. Watchdog Window Periods

CONTROL BIT

DEFAULT

VALUES

WD_LONG_OPEN_TIME

OTP

00 – 200 ms

01 – 600 ms

10 – 2000 ms

11 – 5000 ms

WD_CLOSE_TIME

OTP

00 – 10 ms

01 – 20 ms

10 – 50 ms

11 – 100 ms

WD_OPEN_TIME

OTP

00 – 20 ms

01 – 100 ms

10 – 600 ms

11 – 2000 ms

LP87702-Q1 supports option to disable watchdog. WD_DIS pin function is multiplexed with CLKIN/GPIO2

functions. Watchdog disable option can be selected by setting register bit WD_DIS_CTRL = 1. When

WD_DIS_CTRL = 1, WD is disabled if CLKIN/GPIO2/WD_DIS pin is HIGH and enabled if CLKIN/GPIO2/

WD_DIS pin is LOW. If WD_DIS_CTRL is toggled to disable and re-enable WD, WD starts from Long Open

window after re-enabling.

Default for WD_DIS_CTRL is set in OTP. WD_DIS_CTRL value can be changed via I2C until WD settings are

locked. When WD_LOCK is set to 1, WD is enabled regardless of WD_DIS_CTRL value. WD_DIS_CTRL bit

is protected by write lock. Three consecutive codes have to be written to WD_DIS_UNLOCK_CODE to open

WD_DIS_CTRL for write access.

8.3.9 Device Reset Scenarios

There are four reset methods implemented on the LP87702-Q1:

• Software reset with the SW_RESET bit in the RESET register

• NRST input signal low

• Undervoltage lockout (UVLO) reset from VANA supply

• Watchdog expiration (depending on the watchdog settings)

A SW reset occurs when the SW_RESET bit is set to 1. The bit is automatically cleared after writing. Figure

8-14shows how this event disables all the converters immediately, drives GPO signals low, resets all the register

bits to the default values and the OTP bits are loaded. I2C interface is not reset during a software reset. The host

must wait at least 1.2 ms after writing SW reset until making a new I2C read or write to the device.

If VANA supply voltage falls below the UVLO threshold level or the NRST signal is set low, then all the

converters are disabled immediately, the GPOx signals are driven low, and all the register bits are reset to the

default values. When the VANA supply voltage rises above the UVLO threshold level and the NRST signal rises

above the threshold level, the OTP bits are loaded to the registers and a start-up is initiated according to the

Depending on the watchdog settings, the watchdog expiration can reset the device to the OTP default values.

8.3.10 Diagnostics and Protection Features

The LP87702-Q1 provides four levels of protection features:

• Input and output voltage information. Non-valid voltage sets interrupt or PGx signal:

– Validity of the output voltage of BUCK or BOOST converters

– Validity of VANA, VMON1, and VMON2 input voltages

• Warnings causing interrupt:

– Peak current limit detection in BUCK or BOOST converters

– Thermal warning

• Protection events which are disabling the converters:

– Short-circuit and overload protection for BUCK and BOOST converters

– Input overvoltage protection (VANAOVP)

www.ti.com

LP87702-Q1

SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021

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