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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 72 Page - Texas Instruments |
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LP87702 датащи(HTML) 72 Page - Texas Instruments |
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72 / 99 page  Return to Table 8-9. Figure 8-60. TOP_MASK_1 Register 7 6 5 4 3 2 1 0 I_MEAS_MASK RESERVED SYNC_CLK_M ASK RESERVED TDIE_WARN_M ASK RESERVED R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h Table 8-52. TOP_MASK_1 Register Field Descriptions Bit Field Type Reset Description 7 I_MEAS_MASK R/W 0h Masking for load current measurement ready interrupt I_MEAS_INT in INT_TOP_1 register. 0 – Interrupt generated 1 – Interrupt not generated. (Default from OTP memory) 6-4 RESERVED R/W 0h 3 SYNC_CLK_MASK R/W 0h Masking for external clock detection interrupt SYNC_CLK_INT in INT_TOP_1 register: 0 – Interrupt generated 1 – Interrupt not generated. (Default from OTP memory) 2 RESERVED R/W 0h 1 TDIE_WARN_MASK R/W 0h Masking for thermal warning interrupt TDIE_WARN_INT in INT_TOP_1 register: 0 – Interrupt generated 1 – Interrupt not generated. This bit does not affect TDIE_WARN_STAT status bit in TOP_STATUS register. (Default from OTP memory) 0 RESERVED R/W 0h 8.6.1.1.43 TOP_MASK_2 Register (Offset = 2Ah) [reset = 1h] TOP_MASK_2 is shown in Figure 8-61 and described in Table 8-53. Return to Table 8-9. Figure 8-61. TOP_MASK_2 Register 7 6 5 4 3 2 1 0 RESERVED RESET_REG_ MASK R/W-0h R/W-1h Table 8-53. TOP_MASK_2 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_REG_MASK R/W 1h Masking for register reset interrupt RESET_REG_INT in INT_TOP_2 register: 0 – Interrupt generated 1 – Interrupt not generated. (Default from OTP memory) 8.6.1.1.44 BUCK_MASK Register (Offset = 2Bh) [reset = 0h] BUCK_MASK is shown in Figure 8-62 and described in Table 8-54. Return to Table 8-9. LP87702-Q1 SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021 www.ti.com 72 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702-Q1 |
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