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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 68 Page - Texas Instruments |
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LP87702 датащи(HTML) 68 Page - Texas Instruments |
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68 / 99 page  Figure 8-52. INT_TOP_2 Register (continued) R/W-0h R-0h Table 8-44. INT_TOP_2 Register Field Descriptions Bit Field Type Reset Description 7-1 RESERVED R/W 0h 0 RESET_REG_INT R 0h Latched status bit indicating that either VANA supply voltage has been below undervoltage threshold level or the host has requested a reset (SW_RESET bit in RESET register). The converters have been disabled, and registers are reset to default values and the normal startup procedure is done. Write 1 to clear interrupt. 8.6.1.1.35 INT_BUCK Register (Offset = 22h) [reset = 0h] INT_BUCK is shown in Figure 8-53 and described in Table 8-45. Return to Table 8-9. Figure 8-53. INT_BUCK Register 7 6 5 4 3 2 1 0 RESERVED BUCK1_PG_IN T BUCK1_SC_IN T BUCK1_ILIM_I NT RESERVED BUCK0_PG_IN T BUCK0_SC_IN T BUCK0_ILIM_I NT R/W-0h R-0h R-0h R-0h R/W-0h R-0h R-0h R-0h Table 8-45. INT_BUCK Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h 6 BUCK1_PG_INT R 0h Latched status bit indicating that BUCK1 powergood event has been detected. Write 1 to clear. 5 BUCK1_SC_INT R 0h Latched status bit indicating that the BUCK1 output voltage has fallen below 0.35 V level during operation or BUCK1 output didn't reach 0.35 V level in 1 ms from enable. Write 1 to clear. 4 BUCK1_ILIM_INT R 0h Latched status bit indicating that BUCK1 output current limit has been triggered. Write 1 to clear. 3 RESERVED R/W 0h 2 BUCK0_PG_INT R 0h Latched status bit indicating that BUCK0 powergood event has been detected. Write 1 to clear. 1 BUCK0_SC_INT R 0h Latched status bit indicating that the BUCK0 output voltage has fallen below 0.35 V level during operation or BUCK0 output didn't reach 0.35 V level in 1 ms from enable. Write 1 to clear. 0 BUCK0_ILIM_INT R 0h Latched status bit indicating that BUCK0 output current limit has been triggered. Write 1 to clear. 8.6.1.1.36 INT_BOOST Register (Offset = 23h) [reset = 0h] INT_BOOST is shown in Figure 8-54 and described in Table 8-46. Return to Table 8-9. LP87702-Q1 SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021 www.ti.com 68 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702-Q1 |
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