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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP87702 датащи(PDF) 64 Page - Texas Instruments |
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LP87702 датащи(HTML) 64 Page - Texas Instruments |
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64 / 99 page  Figure 8-46. PG1_FAULT Register 7 6 5 4 3 2 1 0 RESERVED PG1_FAULT_T WARN PG1_FAULT_V ANA PG1_FAULT_V MON2 PG1_FAULT_V MON1 PG1_FAULT_B OOST PG1_FAULT_B UCK1 PG1_FAULT_B UCK0 R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 8-38. PG1_FAULT Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h 6 PG1_FAULT_TWARN R 0h Source for PG1 inactive signal: 0 – TWARN has not set PG1 signal inactive. 1 – TWARN is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when TWARN is valid. 5 PG1_FAULT_VANA R 0h Source for PG1 inactive signal: 0 – VANA has not set PG1 signal inactive. 1 – VANA is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VANA input is valid. 4 PG1_FAULT_VMON2 R 0h Source for PG1 inactive signal: 0 – VMON2 has not set PG1 signal inactive. 1 – VMON2 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VMON2 input is valid. 3 PG1_FAULT_VMON1 R 0h Source for PG1 inactive signal: 0 – VMON1 has not set PG1 signal inactive. 1 – VMON1 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when VMON1 input is valid. 2 PG1_FAULT_BOOST R 0h Source for PG1 inactive signal: 0 – Boost has not set PG1 signal inactive. 1 – Boost is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Boost output is valid. 1 PG1_FAULT_BUCK1 R 0h Source for PG1 inactive signal: 0 – Buck1 has not set PG1 signal inactive. 1 – Buck1 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Buck1 output is valid. 0 PG1_FAULT_BUCK0 R 0h Source for PG1 inactive signal: 0 – Buck0 has not set PG1 signal inactive. 1 – Buck0 is selected for PG1 signal and it has set PG1 signal inactive. This bit can be cleared by writing '1' to this bit when Buck0 output is valid. 8.6.1.1.29 WD_CTRL_1 Register (Offset = 1Ch) [reset = 0h] WD_CTRL_1 is shown in Figure 8-47 and described in Table 8-39. Return to Table 8-9. Figure 8-47. WD_CTRL_1 Register 7 6 5 4 3 2 1 0 WD_CLOSE_TIME WD_OPEN_TIME WD_LONG_OPEN_TIME WD_RESET_CNTR_SEL R/W-0h R/W-0h R/W-0h R/W-0h LP87702-Q1 SNVSAL1C – DECEMBER 2017 – REVISED JUNE 2021 www.ti.com 64 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: LP87702-Q1 |
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